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公开(公告)号：US20090003428A1
公开(公告)日：2009-01-01
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： H03K7/08
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。
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公开(公告)号：US07913101B2
公开(公告)日：2011-03-22
申请号：US11824410
申请日：2007-06-29
申请人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Jae-sun Seo , Ram K. Krishnamurthy
IPC分类号： G06F1/12
CPC分类号： H03K5/135 , H03K2005/00058 , H03K2005/00234 , H03K2005/00241
摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.
摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。
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公开(公告)号：US20140105303A1
公开(公告)日：2014-04-17
申请号：US13649560
申请日：2012-10-11
IPC分类号： H04N7/32
CPC分类号： H04N19/43 , H04N19/567
摘要： In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.
摘要翻译： 根据一些实施例，可以减少使用Haar，SAD和Hadamard变换的运动估计算法的复杂度。 在一些实施例中，与现有技术相比可以减少求和的数量，并且可以用比较操作来替换一些现有的求和。 在一些实施例中，为了平衡延迟和面积或能量或功率考虑，用比较代替添加。
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公开(公告)号：US20090085637A1
公开(公告)日：2009-04-02
申请号：US11906166
申请日：2007-09-28
IPC分类号： H03L5/00
CPC分类号： H03K19/0175 , H03K3/356139
摘要： An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value.
摘要翻译： 一种装置包括：信号接收单元，接收输入信号并呈现在第一信号范围内变化的第一信号; 与所述信号接收单元耦合的信号处理单元，接收所述第一信号并呈现在第二信号范围内变化的第二信号; 以及与信号处理单元耦合的输出单元。 信号处理单元和输出单元接收控制信号。 当控制信号具有第一值时，信号处理单元响应控制信号以向输出单元提供第二信号，并且当控制信号具有第二值时，信号处理单元不向输出单元提供第二信号。 当控制信号具有第一值时，输出单元允许呈现输出信号，并且当控制信号具有第二值时，输出单元确定输出信号为预定值。
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5.发明申请METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) 有权用于芯片上同步电路切换网络的方法，装置和系统（NOC）公开(公告)号：US20150220470A1
公开(公告)日：2015-08-06
申请号：US14126910
申请日：2013-06-28
CPC分类号： G06F13/4022 , G06F13/4282 , G06F15/7825 , H04L12/46 , H04L49/109 , H04L67/10 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，路由器包括多个输入端口和输出端口，其中路由器是源同步混合网络片上（NoC），以基于在路由器之间传送的控制流信号中的转换来实现NoC的路由器之间的通信。 描述和要求保护其他实施例。
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公开(公告)号：US08577948B2
公开(公告)日：2013-11-05
申请号：US12886012
申请日：2010-09-20
申请人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
发明人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
IPC分类号： G06F7/483
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及 如果差值大于阈值，则处理指令执行的第二路径。 基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。 描述和要求保护其他实施例。
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公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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8.发明授权公开(公告)号：US07606062B2
公开(公告)日：2009-10-20
申请号：US12006238
申请日：2007-12-31
IPC分类号： G11C11/40
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
摘要翻译： 描述了关于超低电压存储器位单元的方法和装置。 在一个实施例中，使用对由互补写入字线控制的数据存储节点的冗余路径提供超低电压存储器件。 还描述了其它实施例。
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公开(公告)号：US07352209B2
公开(公告)日：2008-04-01
申请号：US11411647
申请日：2006-04-26
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.
摘要翻译： 电压电平转换器包括静态电压电平转换器和耦合到静态电压电平转换器的分离电平输出电路。 在另一实施例中，电压电平转换器包括静态电压电平转换器，第一晶体管和第二晶体管。 静态电压电平转换器包括输入节点，第一上拉节点，第二上拉节点，逆变器输出节点和输出节点。 第一晶体管耦合到输入节点和第一上拉节点。 第二晶体管耦合到第二上拉节点和逆变器输出节点。
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公开(公告)号：US07272029B2
公开(公告)日：2007-09-18
申请号：US11025778
申请日：2004-12-29
IPC分类号： G11C11/00
摘要： A sense amplifier transition encodes an output signal onto a bus such that the bus signal only transitions when a sensed bit line has a state different from the state of a previously sensed bit line. The sense amplifier includes a storage element that changes state when the bus signal is asserted. The output of the sense amplifier is conditionally inverted based on the state of the storage element.
摘要翻译： 读出放大器转换将输出信号编码到总线上，使得当感测到的位线具有与先前感测的位线的状态不同的状态时，总线信号仅转变。 读出放大器包括当总线信号被断言时改变状态的存储元件。 基于存储元件的状态，读出放大器的输出有条件地反转。
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