公开(公告)号：US20160049195A1

公开(公告)日：2016-02-18

申请号：US14824782

申请日：2015-08-12

申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

IPC分类号： G11C13/00

CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

公开(公告)号：US09466362B2

公开(公告)日：2016-10-11

申请号：US14824782

申请日：2015-08-12

申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

IPC分类号： G11C5/06 ,  G11C13/00

CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

公开(公告)号：US20160336064A1

公开(公告)日：2016-11-17

申请号：US15156113

申请日：2016-05-16

申请人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

发明人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

IPC分类号： G11C13/00 ,  G06N3/08

CPC分类号： G06N3/088 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0069

摘要： Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

摘要翻译： 公开了包括交叉点电阻网络和线路控制电路的神经计算电路。 交叉点电阻网络包括可变电阻单元。 一组可变电阻单元被配置为在导线上产生校正线电流，而其他组的可变电阻单元在其它导线上产生合成线电流。 线路控制电路被配置为从导线接收线电流并产生数字矢量值。 根据对应的合成线电流的电流电平和校正线电流的电流电平之间的差，提供每个数字矢量值。 以这种方式，通过校正线电流的当前电平来校正数字矢量值，以便减少由有限导通到导通状态比率导致的误差。

公开(公告)号：US09934463B2

公开(公告)日：2018-04-03

申请号：US15156113

申请日：2016-05-16

申请人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

发明人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

IPC分类号： G11C11/00 ,  G06N3/08 ,  G11C11/54 ,  G11C13/00

CPC分类号： G06N3/088 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0069

摘要： Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

公开(公告)号：US09356598B2

公开(公告)日：2016-05-31

申请号：US14792163

申请日：2015-07-06

申请人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

发明人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

IPC分类号： G11C7/06 ,  H03K19/23 ,  H03K19/00 ,  G11C13/00 ,  G06F17/50 ,  H03K19/08 ,  H03K19/017 ,  H03K19/21 ,  G11C17/16 ,  G11C17/18

CPC分类号： H03K19/0013 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G11C7/065 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0042 ,  G11C2213/71 ,  G11C2213/79 ,  H03K19/0027 ,  H03K19/01707 ,  H03K19/0813 ,  H03K19/215 ,  Y02P90/265

摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

摘要翻译： 本公开一般涉及用于集成电路（IC）的阈值逻辑元件。 在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。 第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。 差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。 电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。 电阻网络使门限逻辑元件不易受工艺变化的影响。

公开(公告)号：US20160006437A1

公开(公告)日：2016-01-07

申请号：US14792163

申请日：2015-07-06

申请人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

发明人： Sarma Vrudhula ,  Jinghua Yang ,  Niranjan Kulkarni ,  Shimeng Yu

IPC分类号： H03K19/00 ,  G11C13/00

CPC分类号： H03K19/0013 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G11C7/065 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0042 ,  G11C2213/71 ,  G11C2213/79 ,  H03K19/0027 ,  H03K19/01707 ,  H03K19/0813 ,  H03K19/215 ,  Y02P90/265

摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.

摘要翻译： 本公开一般涉及用于集成电路（IC）的阈值逻辑元件。 在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。 第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。 差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。 电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。 电阻网络使门限逻辑元件不易受工艺变化的影响。

公开(公告)号：US09876503B2

公开(公告)日：2018-01-23

申请号：US15390970

申请日：2016-12-27

申请人： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni ,  Joseph Davis

发明人： Sarma Vrudhula ,  Aykut Dengi ,  Niranjan Kulkarni ,  Joseph Davis

IPC分类号： H03K19/20 ,  H03K19/08 ,  H03K19/096 ,  H03K19/21

CPC分类号： H03K19/0813 ,  H03K19/0963 ,  H03K19/21

摘要： A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

公开(公告)号：US08181133B2

公开(公告)日：2012-05-15

申请号：US12401982

申请日：2009-03-11

申请人： Tejaswi Gowda ,  Sarma Vrudhula

发明人： Tejaswi Gowda ,  Sarma Vrudhula

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/504

摘要： Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate.

摘要翻译： 提供了一种用于阈值逻辑电路的组合等价性检查的方法和系统。 在这方面，可以在阈值逻辑门处接收一个或多个输入。 阈值逻辑门的阈值函数可以使用阈值函数的辅因子递归地分解为第一函数和第二函数。 可以基于阈值函数的递归分解来生成阈值逻辑门的布尔函数表示。 阈值逻辑门的生成的布尔函数表示可以是用于阈值逻辑门的产品的最小和（SOP）的最大因子形式表示。 可以基于生成的阈值逻辑门的布尔函数表示，用一个或多个其他逻辑电路来验证阈值逻辑门的逻辑等价。

公开(公告)号：US20100321061A1

公开(公告)日：2010-12-23

申请号：US12867352

申请日：2009-02-13

申请人： Samuel Leshner ,  Sarma Vrudhula

发明人： Samuel Leshner ,  Sarma Vrudhula

IPC分类号： H03K19/23

CPC分类号： H03K19/0813

摘要： Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.

摘要翻译： 提供了阈值逻辑元件的实施例。 优选地，本文所讨论的阈值逻辑元件的实施例具有低泄漏功率和高性能特性。 在优选实施例中，阈值逻辑元件是阈值逻辑锁存器（TLL）。 TLL是一种动态操作的电流模式阈值逻辑单元，可提供快速有效的数字逻辑功能实现。 TLL可以同步或异步操作，并且与标准互补金属氧化物半导体（CMOS）技术完全兼容。

公开(公告)号：US11599779B2

公开(公告)日：2023-03-07

申请号：US16682233

申请日：2019-11-13

申请人： Elham Azari ,  Sarma Vrudhula

发明人： Elham Azari ,  Sarma Vrudhula

IPC分类号： G06N3/04 ,  G06N3/063 ,  G06F13/40

摘要： Disclosed is neural network circuitry having a first plurality of logic cells that is interconnected to form neural network computation units that are configured to perform approximate computations. The neural network circuitry further includes a second plurality of logic cells that is interconnected to form a controller hierarchy that is interfaced with the neural network computation units to control pipelining of the approximate computations performed by the neural network computational units. In some embodiments the neural network computation units include approximate multipliers that are configured to perform approximate multiplications that comprise the approximate computations. The approximate multipliers include preprocessing units that reduce latency while maintaining accuracy.