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1.发明授权
公开(公告)号：US4675808A
公开(公告)日：1987-06-23
申请号：US521401
申请日：1983-08-08
申请人： James M. Grinn , Kevin A. McWethy
发明人： James M. Grinn , Kevin A. McWethy
CPC分类号： G06F12/02 , G11C8/00 , Y02B60/1225
摘要： Disclosed is a computer system (FIG. 1) that is operable with any multiplexed-address memory (200) within a size range of 2.sup.N to 2.sup.N+R memory locations (211). The system has a memory of 2.sup.S locations selected from the predetermined range, and the memory has S/2 multiplexed address input terminals (231). Address bits forming a memory address, generated for example by a processor (400), are multiplexed by a memory controller (300) onto N/2+R address output terminals (314) in two sets of N/2+R address bits. The address bit sets have at least R/2 bits in common. An address bus (250) transports the multiplexed address bits to the memory. The bus has N/2+R address leads (251) connected to the output terminals of the memory controller. S/2 of those address leads are also connected to the address input terminal of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals. Addressing of a different-size memory requires merely connecting the memory to the appropriate address leads of the multiplexed-address bus.
摘要翻译： 公开了一种可在2N至2N + R个存储器位置（211）的大小范围内的任何多路复用地址存储器（200）操作的计算机系统（图1）。 系统具有从预定范围中选择的2S位置的存储器，并且存储器具有S / 2复用地址输入端子（231）。 例如由处理器（400）产生的形成存储器地址的地址位由存储器控制器（300）复用到两组N / 2 + R地址位的N / 2 + R地址输出端（314）上。 地址位集具有至少R / 2位的共同点。 地址总线（250）将复用的地址位传送到存储器。 总线具有连接到存储器控制器的输出端的N / 2 + R地址引线（251）。 这些地址引线的S / 2也连接到存储器的地址输入端。 剩余的地址线未连接。 存储器控制器将预定范围内的任何存储器的地址复用到其输出端子上。 不同尺寸存储器的寻址只需要将存储器连接到多路复用地址总线的适当的地址引线。
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公开(公告)号：US4654820A
公开(公告)日：1987-03-31
申请号：US556350
申请日：1983-11-30
摘要： In a processor system having a central processor and secondary support processor mounted on a backplane board, a separate peripheral interrupt bus is provided for each secondary support processor to give full interrupt priority capability to peripheral devices connected to the support processors. The support processors (110, 120) and certain of the system's peripheral interface circuits (102, 104) are connected to the system's central processor (101) via a primary interrupt bus (105) and other peripheral interface circuits (112, 114, 122) are connected to their associated secondary processors (110, 120) via separate interrupt buses (115, 125) all on the same backplane board. The backplane board is divided into an upper section and a lower section and the primary interrupt bus and the interrupt request and acknowledge terminal pins for all circuit boards are in the lower section. The secondary processor boards and interface circuit boards served by the central processor have interrupt request and acknowledge terminal pins connected to the primary interrupt bus in the lower section. The interrupt request and acknowledge terminal pins for any peripheral interface circuit served by a secondary processor are connected to the associated secondary processor via a secondary interrupt bus formed in the upper section of the backplane and conductors extending between the sections.
摘要翻译： 在具有安装在背板上的中央处理器和辅助支持处理器的处理器系统中，为每个辅助支持处理器提供单独的外围中断总线，以向连接到支持处理器的外围设备提供完整的中断优先级能力。 支持处理器（110,120）和某些系统的外围接口电路（102,104）经由主中断总线（105）和其它外围接口电路（112,114,122）连接到系统的中央处理器（101） ）经由分别在同一背板上的中断总线（115,125）连接到其相关联的辅助处理器（110,120）。 背板分为上部和下部，主中断总线以及所有电路板的中断请求和应答端子引脚位于下部。 中央处理器服务的二级处理器板和接口电路板具有连接到下部的主中断总线的中断请求和应答端子引脚。 由二级处理器服务的任何外围接口电路的中断请求和应答端子引脚经由形成在背板上部的次级中断总线和在各部分之间延伸的导体连接到相关联的辅助处理器。
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公开(公告)号：US4494193A
公开(公告)日：1985-01-15
申请号：US430396
申请日：1982-09-30
CPC分类号： G06F13/4036
摘要： In a communication system which includes a plurality of stations interconnected for communications by a first bus, a second station includes a device, such as a processor, and a resource, such as a memory or a peripheral unit, interconnected for communication by a second bus. An interface mechanism connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses. Deadlock detection circuitry detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource. Deadlock resolution circuitry responds to deadlock detection by disconnecting the device from the second bus to allow the first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource. If the device is operating under program control, the deadlock detection and resolution are transparent to the program.
摘要翻译： 在包括由第一总线进行通信的互连的多个站的通信系统中，第二站包括诸如处理器的设备，以及互连以供第二总线通信的资源，诸如存储器或外围设备 。 将第一总线与第二总线连接的接口机构允许设备通过第二总线访问第一总线，并允许第一站通过第一和第二总线访问资源。 死锁检测电路检测设备访问第一总线并尝试由第一站访问资源的同时尝试。 死锁分辨率电路通过将设备与第二总线断开连接来响应死锁检测，以允许第一站访问资源，并且当第一站停止访问资源时，将设备重新连接到第二总线。 如果设备在程序控制下运行，则死锁检测和分辨率对程序是透明的。
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公开(公告)号：US4751727A
公开(公告)日：1988-06-14
申请号：US876409
申请日：1986-06-20
CPC分类号： G06F12/0692
摘要： A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.
摘要翻译： 多处理器系统包括通过系统通信总线互连的多个站，并且在执行系统任务时配合。 每个站包括通过站通信总线互连的多个可寻址元件。 所有站映射到公共地址空间，每个站的元素映射到地址空间的两个子空间中相似的相对地址：由所有站共享的子空间，以及专用于地址为 公共子空间地址与站标识地址部分组合。 站是对称的：所有站中的像元素被映射到相关子空间中的相似地址。 系统内的寻址是自引用的：一个站通过在站通信总线上放置其公共子空间地址来访问其可寻址元素之一。 每个站的站总线选择性地连接到系统总线，并且站通过在站总线上放置其专用子空间地址来访问另一站的可寻址元件，将其站总线与系统总线接口，并且使得另一站将其 车站总线与系统总线。 一个站被动地访问另一个站的一个元素，而不利用其他站的智能（如果有的话）进行访问。
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公开(公告)号：US4713834A
公开(公告)日：1987-12-15
申请号：US876407
申请日：1986-06-20
CPC分类号： G06F12/0692
摘要： A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.
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公开(公告)号：US4626634A
公开(公告)日：1986-12-02
申请号：US430681
申请日：1982-09-30
CPC分类号： G06F12/0692
摘要： A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space; a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.
摘要翻译： 多处理器系统包括通过系统通信总线互连的多个站，并且在执行系统任务时配合。 每个站包括通过站通信总线互连的多个可寻址元件。 所有站映射到公共地址空间，每个站的元素映射到地址空间的两个子空间中的相似地址; 由所有站共用的子空间，以及专用于站的子空间，其地址是与站识别地址部分组合的公共子空间地址。 站是对称的：所有站中的像元素被映射到相关子空间中的相似地址。 系统内的寻址是自引用的：一个站通过在站通信总线上放置其公共子空间地址来访问其可寻址元素之一。 每个站的站总线选择性地连接到系统总线，并且站通过在站总线上放置其专用子空间地址来访问另一站的可寻址元件，将其站总线与系统总线接口，并且使得另一站将其 车站总线与系统总线。 一个站被动地访问另一个站的一个元素，而不利用其他站的智能（如果有的话）进行访问。
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