公开(公告)号：US20090300575A1

公开(公告)日：2009-12-03

申请号：US12481445

申请日：2009-06-09

申请人： Stephen Kornachuk ,  Carole Lambert ,  James Mali ,  Brian Reed

发明人： Stephen Kornachuk ,  Carole Lambert ,  James Mali ,  Brian Reed

IPC分类号： G06F17/50

CPC分类号： H01L23/528 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.

摘要翻译： 在动态阵列结构中，通过在不规则布线区域的第一和第二侧上分别放置第一和第二规则布线形状来将芯片级布局的一部分内的不规则布线布局区域包围。 一个或多个不规则的线布局形状放置在不规则布线区域内。 在第一规则布线形状和最接近第一规则布线形状的不规则布线区域内的第一外部不规则布线布局形状之间保持第一边缘间隔。 在第二规则布线形状和最接近第二规则布线形状的不规则布线区域内的第二外部不规则布线布局形状之间保持第二边缘间隔。 第一和第二边缘间距被限定以优化规则和不规则布线形状的光刻。

公开(公告)号：US08448102B2

公开(公告)日：2013-05-21

申请号：US12481445

申请日：2009-06-09

申请人： Stephen Kornachuk ,  Carole Lambert ,  James Mali ,  Brian Reed ,  Scott T. Becker

发明人： Stephen Kornachuk ,  Carole Lambert ,  James Mali ,  Brian Reed ,  Scott T. Becker

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： H01L23/528 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.

摘要翻译： 在动态阵列结构中，通过在不规则布线区域的第一和第二侧上分别放置第一和第二规则布线形状来将芯片级布局的一部分内的不规则布线布局区域包围。 一个或多个不规则的线布局形状放置在不规则布线区域内。 在第一规则布线形状和最接近第一规则布线形状的不规则布线区域内的第一外部不规则布线布局形状之间保持第一边缘间隔。 在第二规则布线形状和最接近第二规则布线形状的不规则布线区域内的第二外部不规则布线布局形状之间保持第二边缘间隔。 第一和第二边缘间距被限定以优化规则和不规则布线形状的光刻。