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公开(公告)号：US20130022133A1
公开(公告)日：2013-01-24
申请号：US13341916
申请日：2011-12-31
IPC分类号： H04L25/00
摘要： A balun structure is disclosed having positive and negative going signal paths coupled to a ninety degree hybrid. The positive signal path has a circuit trace and a phase shaper structure that provides three hundred and sixty degrees of phase shift at Port 1 of the hybrid. The negative going signal path has a circuit trace and a second order phase shaper that provides four hundred and fifty degrees of phase shift at Port 2 of the hybrid. Port 1 is coupled to Port 3 of the hybrid and functions as an output port. The first order phase shaper and the second order phase shaper compensate for the signal loss caused by a signal cable coupled to the output port and provide a frequency band from DC to at least 15 GHz and a transient response having less than ten percent pre-shoot.
摘要翻译： 公开了一种平衡 - 不平衡变换器结构，其具有耦合到九十度混合的正向和负向信号路径。 正信号路径具有电路迹线和相位整形器结构，其在混合端口1处提供三百六十度的相移。 负向信号路径具有电路迹线和二阶相位成形器，其在混合物的端口2处提供四百五十度的相移。 端口1耦合到混合端口3，并用作输出端口。 第一阶相位整形器和二阶相位整形器补偿由耦合到输出端口的信号电缆引起的信号损耗，并提供从DC到至少15GHz的频带和具有小于10％的预拍摄的瞬态响应 。
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公开(公告)号：US5307024A
公开(公告)日：1994-04-26
申请号：US920076
申请日：1992-07-27
申请人： Arthur J. Metz , James S. Lamb
发明人： Arthur J. Metz , James S. Lamb
IPC分类号： B01J31/24 , C07B61/00 , C07C45/50 , C07C47/02 , C07F9/6568 , C07F15/00 , H03F1/32 , H03F3/45
CPC分类号： C07C45/50 , B01J31/248 , C07F15/008 , C07F9/65683 , H03F1/3211 , H03F3/45098 , H03F3/45197 , B01J2231/321 , B01J2531/822 , H03F2203/45176 , H03F2203/45221 , H03F2203/45454 , H03F2203/45458 , H03F2203/45496 , H03F2203/45648 , H03F2203/45668
摘要： An all NPN transistor level-shifting differential amplifier has first and second identical amplifier halves, in which each amplifier half includes a passive voltage-shifting network coupled between a load and a current source. A main amplifier has a single-ended voltage input and an output coupled to the first node of the voltage shifting network. An output amplifier has a single-ended current output and an input coupled to the second node of the voltage shifting network. The main amplifier and output amplifiers are coupled together such that a portion of the bias and signal currents flowing through the output amplifier is reused and flows through the main amplifier, reducing bias current and power requirements. The first and second amplifier halves are coupled together with a gain-setting emitter resistor. In addition to reducing the power requirements of the amplifier, the feedback configuration of the level-shifting amplifier also increases linearity over prior art level-shifting amplifiers.
摘要翻译： 所有NPN晶体管电平移位差分放大器具有第一和第二相同的放大器半部，其中每个放大器一半包括耦合在负载和电流源之间的无源电压移动网络。 主放大器具有单端电压输入和耦合到电压转换网络的第一节点的输出。 输出放大器具有单端电流输出和耦合到电压转换网络的第二节点的输入。 主放大器和输出放大器耦合在一起，使得流过输出放大器的偏置和信号电流的一部分被重新使用并流过主放大器，减少了偏置电流和功率需求。 第一和第二放大器一半与增益设置发射极电阻耦合在一起。 除了降低放大器的功率需求之外，电平移位放大器的反馈配置还提高了现有技术的电平移位放大器的线性度。
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3.发明授权Variable transient response control for linear integrated-circuit high-frequency amplifiers 失效线性集成电路高频放大器的可变瞬态响应控制
公开(公告)号：US4739283A
公开(公告)日：1988-04-19
申请号：US20270
申请日：1987-03-02
申请人： Arthur J. Metz , James S. Lamb
发明人： Arthur J. Metz , James S. Lamb
CPC分类号： H03G3/18 , H03G1/0052
摘要： A variable transient response control for linear integrated-circuit high-frequency amplifiers comprises a variable equivalent resistive damping network interposed in the signal transmission path, and an electronic control circuit therefor. The resistive network includes preferably Schottky diodes having low inductance and a determinable equivalent resistance in the forward conducting condition.
摘要翻译： 用于线性集成电路高频放大器的可变瞬态响应控制器包括插入在信号传输路径中的可变等效电阻阻尼网络及其电子控制电路。 电阻网络优选地包括在正向导通条件下具有低电感和可确定的等效电阻的肖特基二极管。
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公开(公告)号：US4890067A
公开(公告)日：1989-12-26
申请号：US337677
申请日：1989-04-13
申请人： James S. Lamb
发明人： James S. Lamb
CPC分类号： H03F3/45197 , H03F3/45103 , H03F2203/45024 , H03F2203/45031
摘要： An f.sub.T doubler amplifier having a Darlington type common base stage is provided wherein the fast current contributions from the f.sub.T doubler are passed through the slow path of the Darlington common base stage, and the slow current contributions from the f.sub.T doubler are passed through the fast path of the Darlington common base in order that the delay of each current contribution is more closely matched. In this way, the distributed nature of the amplifier and resultant phase distortion are minimized and transient response is improved.
摘要翻译： 提供具有达林顿型公共基准级的fT倍频放大器，其中来自fT倍频器的快速电流贡献通过达林顿公共基极级的慢路径，并且来自fT倍频器的慢电流贡献通过快速路径 的达林顿共同基地，以便每个当前的贡献的延迟更紧密地匹配。 以这种方式，放大器的分布特性和合成的相位失真被最小化并且瞬态响应得到改善。
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公开(公告)号：US4808936A
公开(公告)日：1989-02-28
申请号：US172875
申请日：1988-03-25
申请人： James S. Lamb
发明人： James S. Lamb
摘要： A clock-delay circuit for a sinusoidal clock output includes a pair of current amplifiers, each connected to the clock output, wherein one of the amplifiers generates an amplified signal in phase with the clock output and the other generates a signal shifted in phase by 90.degree.. Both signals are multiplied by control signals to alter their respective amplitudes prior to summation of both multiplier outputs. The sum of the multiplier outputs will be a sinusoidal waveform whose phase depends upon the control currents in the multipliers which are set by the user. Thus, the circuit provides a user-controlled continuously variable delay for a sinusoidal clock.
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公开(公告)号：US4513417A
公开(公告)日：1985-04-23
申请号：US445342
申请日：1982-11-29
申请人： James S. Lamb , Warren K. Wimmer
发明人： James S. Lamb , Warren K. Wimmer
摘要： A restart circuit for a digital processor is disclosed. A regularly serviced processor signal is continuously monitored and if an intermittant soft failure of the processor occurs, causing the processor signal to go high or low or toggle in an irregular fashion, a restart pulse is automatically generated. Thus, with the occurrence of a soft failure, the operator no longer has to manually reset the processor system.
摘要翻译： 公开了一种用于数字处理器的重启电路。 持续监控经常维护的处理器信号，并且如果处理器发生间歇性软故障，导致处理器信号变为高电平或低电平或以不规则方式切换，则自动产生重启脉冲。 因此，随着软故障的发生，操作者不再需要手动重置处理器系统。
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公开(公告)号：US08611436B2
公开(公告)日：2013-12-17
申请号：US13341916
申请日：2011-12-31
IPC分类号： H04B3/00
摘要： A balun structure is disclosed having positive and negative going signal paths coupled to a ninety degree hybrid. The positive signal path has a circuit trace and a phase shaper structure that provides three hundred and sixty degrees of phase shift at Port 1 of the hybrid. The negative going signal path has a circuit trace and a second order phase shaper that provides four hundred and fifty degrees of phase shift at Port 2 of the hybrid. Port 1 is coupled to Port 3 of the hybrid and functions as an output port. The first order phase shaper and the second order phase shaper compensate for the signal loss caused by a signal cable coupled to the output port and provide a frequency band from DC to at least 15 GHz and a transient response having less than ten percent pre-shoot.
摘要翻译： 公开了一种平衡 - 不平衡变换器结构，其具有耦合到九十度混合的正向和负向信号路径。 正信号路径具有电路迹线和相位整形器结构，其在混合端口1处提供三百六十度的相移。 负向信号路径具有电路迹线和二阶相位成形器，其在混合物的端口2处提供四百五十度的相移。 端口1耦合到混合端口3，并用作输出端口。 第一阶相位整形器和二阶相位成形器补偿由耦合到输出端口的信号电缆引起的信号损耗，并提供从DC到至少15GHz的频带和具有小于10％的预拍摄的瞬态响应 。
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公开(公告)号：US4663610A
公开(公告)日：1987-05-05
申请号：US801118
申请日：1985-11-22
申请人： Arthur J. Metz , James S. Lamb
发明人： Arthur J. Metz , James S. Lamb
CPC分类号： H03M1/745
摘要： A serial DAC comprises two shift registers having their data input terminals connected together for receiving serial binary data. The shift registers are clocked alternately, whereby each shift register is clocked at substantially half the rate at which data is applied to the data input terminals of the shift registers. Two current switches are associated with the shift registers respectively, each switch being operative to steer input current to one of two output terminals if the data output of the associated shift register is a digital 1 and to steer input current to the other output terminal if the data output is a digital 0. Two current sources supply equal, constant currents to input terminals of the two current switches respectively. A third current switch has two output terminals connected to the input terminals of the first and second switches respectively, and is operative to steer its input current to its two output terminals in alternating fashion, switching between its two output terminals at the same rate as the shift registers are clocked. A third constant current source supplies the third switch with an input current equal to that supplied by the first and second sources, and the current supplied by the third current source is added alternately to the current supplied by the first source and the current supplied by the second source.
摘要翻译： 串行DAC包括两个移位寄存器，其数据输入端连接在一起用于接收串行二进制数据。 移位寄存器交替地进行时钟输入，由此每个移位寄存器的时钟基本上是将数据施加到移位寄存器的数据输入端的速率的一半。 两个电流开关分别与移位寄存器相关联，如果相关联的移位寄存器的数据输出是数字1，则每个开关可操作以将输入电流转向两个输出端中的一个，并且如果输入电流 数据输出为数字0.两个电流源分别为两个电流开关的输入端提供相等的恒定电流。 第三电流开关具有分别连接到第一和第二开关的输入端子的两个输出端子，并且可操作地以其交替方式将其输入电流转向其两个输出端子，以与其相同的速率在其两个输出端子之间切换 移位寄存器是时钟。 第三恒流源向第三开关提供等于由第一和第二源提供的输入电流的输入电流，并且将由第三电流源提供的电流交替地添加到由第一源提供的电流和由第一源提供的电流 第二来源。
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