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    Dual level polysilicon single transistor-capacitor memory array
    2.
    发明授权
    Dual level polysilicon single transistor-capacitor memory array 失效
    双电平多晶硅单晶体管 - 电容存储阵列

    公开(公告)号：US4887135A

    公开(公告)日：1989-12-12

    申请号：US694487

    申请日：1985-01-24

    申请人： Glen T. Cheney ,  Howard C. Kirsch ,  James T. Nelson ,  James H. Stefany

    发明人： Glen T. Cheney ,  Howard C. Kirsch ,  James T. Nelson ,  James H. Stefany

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10805

    摘要： A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.

    摘要翻译： 提供了自对准的一个晶体管 - 电容器存储单元，其使用具有分离的漏极和源极区域的n沟道MOS晶体管，其中第一级多晶硅导体耦合到电容器的顶板，并且分离的第二级多晶硅导体耦合到栅极 和晶体管的漏极。 与仅使用一个级别的导体的类似的存储器单元相比，可以减小存储单元的尺寸。

    PROXIMITY ORDER PROCESSING SYSTEM
    3.
    发明申请
    PROXIMITY ORDER PROCESSING SYSTEM 审中-公开
    接近订单处理系统

    公开(公告)号：US20080070569A1

    公开(公告)日：2008-03-20

    申请号：US11470846

    申请日：2006-09-07

    申请人： John T. Shelley ,  Aaron M. Shelley ,  Adam M. Engesath ,  James T. Nelson ,  Mark L. Robinson

    发明人： John T. Shelley ,  Aaron M. Shelley ,  Adam M. Engesath ,  James T. Nelson ,  Mark L. Robinson

    IPC分类号： H04Q7/20

    CPC分类号： G06Q30/06 ,  H04L67/04

    摘要： A proximity-based order processing system provides a way for a customer of a restaurant or other retail establishment to set up a default order for food or other goods or services via a web page interface. The customer is issued a portable wireless communication device, such as an active RFID device, having an order-confirmation button. If the button is pressed while the portable unit is in range of a reader unit in the retail establishment, the portable unit transmits an order confirmation signal to the reader unit. Upon receipt of the order confirmation signal, a order handling computer system confirms that a default order on file for the customer and sufficient funds are available in the user's monetary account. If the default order is on file and the funds are sufficient, the customer's order is processed and made ready for pickup. In this manner, the customer need not stand in line to wait to place or pay for an order.

    摘要翻译： 基于邻近的订单处理系统为餐厅或其他零售机构的顾客提供了一种通过网页界面设置食品或其他商品或服务的默认订单的方式。 该客户被发行便携式无线通信设备，诸如有源RFID设备，具有订单确认按钮。 如果便携式单元在零售店内的读取器单元的范围内按下按钮，则便携式单元向读取器单元发送订单确认信号。 在接收到订单确认信号时，订单处理计算机系统确认用户的货币账户中存在用于客户的文件的默认订单和足够的资金。 如果默认订单是文件，资金足够，客户的订单将被处理并准备好提货。 以这种方式，客户不必排队等待下订单或支付订单。

    MOS Dynamic memory in a diffusion current limited semiconductor structure
    6.
    发明授权
    MOS Dynamic memory in a diffusion current limited semiconductor structure 失效
    MOS在扩散电流限制半导体结构中的动态存储器

    公开(公告)号：US4216489A

    公开(公告)日：1980-08-05

    申请号：US5639

    申请日：1979-01-22

    申请人： James T. Clemens ,  Dinesh A. Mehta ,  James T. Nelson ,  Charles W. Pearce ,  Robert C. Sun

    发明人： James T. Clemens ,  Dinesh A. Mehta ,  James T. Nelson ,  Charles W. Pearce ,  Robert C. Sun

    IPC分类号： G11C11/35 ,  G11C11/404 ,  H01L27/108 ,  H01L27/02

    CPC分类号： G11C11/404 ,  G11C11/35 ,  H01L27/10805 ,  Y10S148/07

    摘要： In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer (14) of a layered structure (11). The semiconductor layer (14) is grown epitaxially with a relatively low dopant concentration on a semiconductor substrate (12) with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics.

    摘要翻译： 在动态MOS（金属氧化物半导体）随机存取存储器中，通过最小化少数载流子产生型电流来减少耗尽存储电荷的反向偏置漏电流。 通过如此最小化这些电流，泄漏电流成为少数载流子扩散电流的主导。 存储器理想地形成在层状结构（11）的上半导体层（14）中。 在半导体衬底（12）上以相对低的掺杂剂浓度外延生长半导体层（14），其掺杂浓度相同，并且比外延生长层大约三个数量级。 外延生长的结构有利地适用于存储器电路，因为其可以形成非常低的漏电流。 该材料通过其分层结构进一步提供了优化动态存储器件特性的基础。