公开(公告)号：US5898744A

公开(公告)日：1999-04-27

申请号：US722433

申请日：1996-10-07

Applicant: James W. Kimbrow ,  Raymond P. Voith ,  Matthew A. Pendleton

Inventor： James W. Kimbrow ,  Raymond P. Voith ,  Matthew A. Pendleton

IPC: H04J3/06 ,  H04J3/07 ,  H03D3/24 ,  H04L7/00

CPC classification number: H04J3/07 ,  H04J3/0632

Abstract: A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

Abstract translation: 一种用于在接收机处恢复ADSL（非对称数字用户线路）通信系统中的时钟以匹配发送信号的频率的方法。 基于数字锁相环（DPLL）的时钟用于调整收发器单元中FIFO（先进先出）存储器（26）的数据读取访问频率。 根据预定偏移值来调整频率，其中偏移值指示FIFO存储器（26）中的读取位置与写入位置之间的相对差。 预定偏移值定义FIFO存储器（26）中的工作点或标称数据位置。 FIFO相位检测器（31）确定并影响频率调整，以将FIFO存储器保持在大约工作点。 一个实施例提供了用于接收的ADSL子信道的时钟恢复和用于恢复用于信道控制的16kHz时钟的装置。

公开(公告)号：US5825768A

公开(公告)日：1998-10-20

申请号：US723437

申请日：1996-09-30

Applicant: James W. Kimbrow ,  Raymond P. Voith

Inventor： James W. Kimbrow ,  Raymond P. Voith

IPC: H04L27/26 ,  H04N5/44 ,  H04N7/14 ,  H04Q3/58 ,  H04J1/06

CPC classification number: H04L27/2626 ,  H04N21/2385 ,  H04N21/6125 ,  H04N5/4401 ,  H04N7/148 ,  H04Q3/58 ,  H04N21/64307 ,  H04Q2213/13034 ,  H04Q2213/13103 ,  H04Q2213/1319 ,  H04Q2213/13199 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13353

Abstract: An interface (50) for a transceiver (5) for use in an asymmetric digital subscriber line (ADSL) system includes a routing table (200) which includes addresses of locations in a frame memory (150). When the transceiver (5) is operated as a central office transmitter input port data is received from several input ports. The routing table (200) addresses assign locations in the frame memory (150), corresponding to channels in the ADSL frame, which may be arbitrarily assigned. A control circuit (148) services the input ports by transferring data between the input ports and the address selected by the routing table (200). When operated as a remote terminal receiver, the transceiver (5) uses a routing table addressing the system except that the ports become output ports and frame memory (150) locations provide data to the output ports.

Abstract translation: 用于非对称数字用户线（ADSL）系统的用于收发器（5）的接口（50）包括路由表（200），其包括帧存储器（150）中的位置的地址。 当收发器（5）作为中心局发射机操作时，从多个输入端口接收数据。 路由表（200）对与可以任意分配的ADSL帧中的信道相对应地分配帧存储器（150）中的位置。 控制电路（148）通过在输入端口和由路由表（200）选择的地址之间传送数据来为输入端口提供服务。 当作为远程终端接收器操作时，收发器（5）使用寻址系统的路由表，除了端口变为输出端口，并且帧存储器（150）位置向输出端口提供数据。