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公开(公告)号：US20090049331A1
公开(公告)日：2009-02-19
申请号：US11887106
申请日：2005-10-03
IPC分类号： G06F11/20
CPC分类号： G06F11/261 , G06F17/5045 , Y02T10/82
摘要： A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.
摘要翻译： 选择错误检测电路应放置在集成电路中的方法，使用注入到测试设计中的错误的参考和测试设计的仿真，然后扇出对这些注入错误进行的分析，以识别误差传播特性。 因此，可以识别传播错误很可能表现自身或者保护关键体系结构状态或哪个保护状态没有被其他方式保护的寄存器，从而实现错误检测机制的有效部署。 在集成电路内，根据检测到的集成电路的当前状态，来自非活动电路元件的输出信号可能经受隔离门控。 因此，出现软错误的无效电路元件具有不适当的输出信号，从而不能到达集成电路的其余部分，从而减少错误的操作。
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公开(公告)号：US20080036487A1
公开(公告)日：2008-02-14
申请号：US11878882
申请日：2007-07-27
IPC分类号： G01R31/26
CPC分类号： G01R31/31708 , G01R31/287
摘要： An integrated circuit is provided with latency detecting circuitry for detecting signal generation latency within one or more functional circuits and in response thereto to generate a wearout response. The wearout response can take a variety of different forms such as reducing the operating frequency, increasing the operating voltage, operating task allocation within a multiprocessor system, manufacturing test binning and other wearout responses.
摘要翻译： 集成电路设置有等待时间检测电路，用于检测一个或多个功能电路内的信号产生等待时间，并响应于此产生一个耗损响应。 疲劳响应可以采取各种不同的形式，例如降低工作频率，增加工作电压，在多处理器系统内的操作任务分配，制造测试合并和其他损耗响应。
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公开(公告)号：US08219885B2
公开(公告)日：2012-07-10
申请号：US12226108
申请日：2006-08-15
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/1004
摘要： A data processing system includes a register file having a plurality of registers storing respective register data values and an associated register value cache having a plurality of storage locations storing corresponding cache data values. There are fewer cache data values than registers. When a register is to be read, both the register data value and, if present, a cache data value from a corresponding storage location within the register value cache are read and compared by a comparator. This generates a match signal which indicates if the data values do not match that one of the data values is in error. The match signal stalls the processing and a CRC code initially stored with the cache data value and recalculated based upon the read cache data value are compared to determine whether or not the cache data value has changed since it was stored. If the cache data value has not changed, then it is correct and is output instead of the register data value. Alternatively, if the cache data value has changed, then the register data value is output.
摘要翻译： 数据处理系统包括具有存储相应寄存器数据值的多个寄存器的寄存器文件和具有多个存储对应的高速缓存数据值的存储位置的相关联的寄存器值高速缓存。 缓存数据值比寄存器少。 当要读取寄存器时，寄存器数据值和寄存器值高速缓存中相应存储位置的高速缓存数据值（如果存在）都被比较器读取并比较。 这产生一个匹配信号，它指示数据值是否与数据值之一不符。 匹配信号使处理停止，并且比较最初存储有高速缓存数据值并基于读取的高速缓存数据值重新计算的CRC码，以确定高速缓存数据值是否已经被存储以来已经改变。 如果缓存数据值没有改变，那么它是正确的并且是输出而不是寄存器数据值。 或者，如果缓存数据值已经改变，则输出寄存器数据值。
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4.发明授权Insertion of error detection circuits based on error propagation within integrated circuits 有权基于集成电路内的误差传播插入误差检测电路公开(公告)号：US07926021B2
公开(公告)日：2011-04-12
申请号：US11887106
申请日：2005-10-03
IPC分类号： G06F17/50
CPC分类号： G06F11/261 , G06F17/5045 , Y02T10/82
摘要： A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.
摘要翻译： 选择错误检测电路应放置在集成电路中的方法，使用注入到测试设计中的错误的参考和测试设计的仿真，然后扇出对这些注入错误进行的分析，以识别误差传播特性。 因此，可以识别传播错误很可能表现自身或者保护关键体系结构状态或哪个保护状态没有被其他方式保护的寄存器，从而实现错误检测机制的有效部署。 在集成电路内，根据检测到的集成电路的当前状态，来自非活动电路元件的输出信号可能经受隔离门控。 因此，出现软错误的无效电路元件具有不适当的输出信号，从而不能到达集成电路的其余部分，从而减少错误的操作。
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公开(公告)号：US20090292977A1
公开(公告)日：2009-11-26
申请号：US12226108
申请日：2006-08-15
CPC分类号： G06F11/167 , G06F11/1004
摘要： A data processing system includes a register file (2) having a plurality of registers storing respective register data values and an associated register value cache (12) having a plurality of storage locations (14) storing corresponding cache data values. There are fewer cache data values than registers. When a register is to be read, both the register data value and, if present, a cache data value from a corresponding storage location (14) within the register value cache (12) are read and compared by a comparator (18). This generates a match signal which indicates if the data values do not match that one of the data values is in error. The match signal stalls the processing and a CRC code initially stored with the cache data value and recalculated based upon the read cache data value are compared to determine whether or not the cache data value has changed since it was stored. If the cache data value has not changed, then it is correct and is output instead of the register data value. Alternatively, if the cache data value has changed, then the register data value is output.
摘要翻译： 数据处理系统包括具有存储相应寄存器数据值的多个寄存器的寄存器文件（2）和具有存储对应高速缓存数据值的多个存储位置（14）的关联寄存器值缓存（12）。 缓存数据值比寄存器少。 当要读取寄存器时，寄存器数据值和寄存器值高速缓冲存储器（12）中对应的存储位置（14）的高速缓存数据值（如果存在）都被比较器（18）比较。 这产生一个匹配信号，它指示数据值是否与数据值之一不符。 匹配信号使处理停止，并且比较最初存储有高速缓存数据值并基于读取的高速缓存数据值重新计算的CRC码，以确定高速缓存数据值是否已经被存储以来已经改变。 如果缓存数据值没有改变，那么它是正确的并且是输出而不是寄存器数据值。 或者，如果缓存数据值已经改变，则输出寄存器数据值。
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