公开(公告)号：US5319253A

公开(公告)日：1994-06-07

申请号：US985808

申请日：1992-12-02

申请人： Jei-Hwan You

发明人： Jei-Hwan You

IPC分类号： G11C11/403 ,  G11C7/06 ,  G11C7/22 ,  G11C11/406 ,  G11C11/409 ,  H03K5/135 ,  H03K3/86 ,  H03K5/14

CPC分类号： G11C7/22 ,  G11C7/065 ,  H03K5/135

摘要： A semiconductor memory device with data retention function to retain data is provided with a sense amplifier control signal generating circuit comprising a switching circuit controlled by a data retention mode detection signal so as to make the time interval between enabling of a word line and starting of an N- or P-type sense amplifier longer in data retention mode than in normal mode. Thus the inventive circuit generates a sense amplifier control signal whose delay time differs in the normal and data retention modes, so that the data retention mode is performed without influencing the operational speed, the charge sharing is sufficiently achieved in the data retention mode, and the direct current flowing is prevented.

摘要翻译： 具有保留数据的具有数据保持功能的半导体存储器件具有读出放大器控制信号发生电路，该读出放大器控制信号发生电路包括由数据保持模式检测信号控制的开关电路，以便使得字线的启用和开始之间的时间间隔 N型或P型读出放大器的数据保持模式比正常模式下更长。 因此，本发明的电路产生读出放大器控制信号，其延时在正常和数据保持模式下不同，从而在不影响操作速度的情况下执行数据保持模式，在数据保持模式下充分实现电荷共享， 防止直流流动。

公开(公告)号：US5523978A

公开(公告)日：1996-06-04

申请号：US269607

申请日：1994-07-05

申请人： Sei-Seung Yoon ,  Jei-Hwan You

发明人： Sei-Seung Yoon ,  Jei-Hwan You

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/22 ,  G11C13/00

CPC分类号： G11C7/22 ,  G11C5/143

摘要： The present invention relates to a semiconductor memory device and more particularly to a power supply voltage detecting circuit of a semiconductor memory device which senses a voltage level of the power supply voltage. A power supply voltage detecting circuit of the present invention includes a circuit for generating a power supply voltage detecting signal by receiving a power supply voltage and a control circuit for generating a control signal in order to operate the circuit for generating the power supply voltage detecting signal when being in a specific mode state. The power supply voltage detecting circuit according to the present invention can reduce power consumption by cutting off a standby-current, since the power supply voltage detecting circuit is enabled during an activation of a chip. This allows the output signal of the power supply voltage detecting circuit to have an accurate voltage level of a power supply voltage or a ground voltage, so that chip operation speed can be improved and the effectiveness of the chip can be improved by removing noises.

摘要翻译： 本发明涉及一种半导体存储器件，更具体地说，涉及一种感测电源电压的电压电平的半导体存储器件的电源电压检测电路。 本发明的电源电压检测电路包括：通过接收电源电压产生电源电压检测信号的电路和用于产生控制信号的控制电路，以便操作用于产生电源电压检测信号的电路 当处于特定模式状态时。 根据本发明的电源电压检测电路可以通过切断待机电流来降低功耗，因为在芯片激活期间电源电压检测电路被使能。 这允许电源电压检测电路的输出信号具有电源电压或接地电压的精确电压电平，从而可以提高芯片操作速度，并且可以通过去除噪声来提高芯片的有效性。

公开(公告)号：US5471480A

公开(公告)日：1995-11-28

申请号：US50779

申请日：1993-04-22

申请人： Jei-Hwan You

发明人： Jei-Hwan You

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G11C29/40 ,  H01L21/66

CPC分类号： G11C29/40

摘要： A parallel test circuit is provided in a semiconductor memory chip for use during both a wafer test and a package test. The parallel test circuit operates to automatically reduce the number of test output pins associated with a single package test to thereby increase the number of packages that can be tested simultaneously. The parallel test circuit includes a selector for limiting the number of output pads which may be activated during a package test run. The selector is responsive to a wafer test enable signal, from a selection control circuit, to control output pad selection.

摘要翻译： 在半导体存储芯片中提供并行测试电路，以在晶片测试和封装测试期间使用。 并行测试电路用于自动减少与单个封装测试相关联的测试输出引脚的数量，从而增加可同时测试的封装数量。 并行测试电路包括用于限制在封装测试运行期间可以被激活的输出焊盘的数量的选择器。 选择器响应来自选择控制电路的晶片测试使能信号来控制输出焊盘选择。

公开(公告)号：US5283764A

公开(公告)日：1994-02-01

申请号：US990914

申请日：1992-12-15

申请人： Myong-Jae Kim ,  Jei-Hwan You

发明人： Myong-Jae Kim ,  Jei-Hwan You

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A refresh timer suitable for use in a semiconductor memory device which has a refresh mode of operation which is enabled by a refresh enable clock signal, and which utilizes an operating voltage having a plurality of different operating levels, Vi, where i=1-n, and n is an integer equal to or greater than two. The refresh timer includes a first circuit responsive to the operating voltage for generating a plurality of output voltage signals corresponding to the plurality of different operating voltage levels, respectively. The first circuit includes a plurality of individual voltage detection circuits corresponding to the plurality of different operating voltage levels, respectively, with each ith one of the voltage detection circuits being adapted to detect whether the operating voltage is at the corresponding ith level, and to drive the corresponding ith one of the output voltage signals high when it is detected that the operating voltage is at the corresponding ith level. The refresh timer also includes additional circuitry responsive to the refresh enable clock signal and the ith one of the output voltage signals which was last driven high by the first circuit, for generating a refresh cycle time control signal having a constant period, regardless of the level of the operating voltage.

摘要翻译： 一种适用于半导体存储器件的刷新定时器，其具有通过刷新使能时钟信号使能的刷新操作模式，并且利用具有多个不同操作电平的工作电压Vi，其中i = 1-n ，n为2以上的整数。 刷新定时器包括响应于工作电压的第一电路，用于分别产生对应于多个不同工作电压电平的多个输出电压信号。 第一电路包括分别对应于多个不同工作电压电平的多个单独的电压检测电路，其中每个第一个电压检测电路适于检测工作电压是否处于相应的第i级，并驱动 当检测到工作电压处于相应的第i级时，相应的第一个输出电压信号为高电平。 刷新定时器还包括响应于刷新使能时钟信号和最后被第一电路驱动为高电平的输出电压信号中的第一个的附加电路，用于产生具有恒定周期的刷新周期时间控制信号，而不管电平如何 的工作电压。

公开(公告)号：US5583818A

公开(公告)日：1996-12-10

申请号：US358120

申请日：1994-12-19

申请人： Jei-Hwan You ,  Dong-Soo Jun

发明人： Jei-Hwan You ,  Dong-Soo Jun

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A self-refresh method and refresh control circuit of a semiconductor memory device, wherein after the self-refresh mode starts, the burst refresh mode is performed prior to the self-refresh mode; or the self-refresh mode is performed immediately after going into the self-refresh mode, and the burst refresh mode is performed at the completion of the self-refresh mode, and then the burst refresh mode is converted to the normal access mode; or the burst refresh mode is performed before and after the self-refresh mode, thereby shortening a refresh regulation time and securing a stable refresh of the memory cells.

摘要翻译： 一种半导体存储器件的自刷新方法和刷新控制电路，其中在自刷新模式开始之后，在自刷新模式之前执行突发刷新模式; 或者在进入自刷新模式后立即执行自刷新模式，并且在完成自刷新模式时执行突发刷新模式，然后将突发刷新模式转换为正常访问模式; 或者在自刷新模式之前和之后执行突发刷新模式，从而缩短刷新调节时间并确保存储单元的稳定刷新。