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公开(公告)号：US08176225B2
公开(公告)日：2012-05-08
申请号：US12756310
申请日：2010-04-08
摘要： A method and apparatus for distributing events. In one embodiment, the method includes a bus concurrently transmitting a first event-signal and a first event-identification (event-ID); wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur. The first event-ID corresponds to the first event-signal.
摘要翻译： 一种用于分发事件的方法和装置。 在一个实施例中，该方法包括同时发送第一事件信号和第一事件识别（事件ID）的总线; 其中所述第一事件信号在活动时指示已发生第一事件正在发生或应当发生。 第一事件ID对应于第一事件信号。
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公开(公告)号：US08140723B2
公开(公告)日：2012-03-20
申请号：US12264538
申请日：2008-11-04
CPC分类号： F02D41/263 , F02D41/20 , F02D41/26 , F02P5/15 , Y02T10/46
摘要： An apparatus and method of scheduling signals. In one embodiment, the method includes a first circuit receiving a first plurality of reference values. The first circuit selects a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory. The first circuit compares the selected reference value to a first match value.
摘要翻译： 一种调度信号的装置和方法。 在一个实施例中，该方法包括接收第一多个参考值的第一电路。 第一电路根据存储在存储器中的第一参考标识符（ID）选择来自第一多个的参考值。 第一电路将所选择的参考值与第一匹配值进行比较。
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公开(公告)号：US08085066B2
公开(公告)日：2011-12-27
申请号：US12582757
申请日：2009-10-21
IPC分类号： H03K19/0175
CPC分类号： G06F13/4072
摘要： A microprocessor control unit (MCU) is mounted on a printed circuit board. The MCU includes first and second clocked serial interface (CSI) circuits. The first CSI circuit is configured to serially transmit a first xCP packet to a first encoder circuit, which in turn is configured to generate an encoded first xCP packet as a function of the first xCP packet and a first clock signal. A first low voltage differential signal (LVDS) circuit is coupled to the first encoder circuit and configured to serially receive the encoded first xCP packet therefrom. The first LVDS circuit is configured to generate a first differential signal as a function of the encoded first xCP packet.
摘要翻译： 微处理器控制单元（MCU）安装在印刷电路板上。 MCU包括第一和第二时钟串行接口（CSI）电路。 第一CSI电路被配置为将第一xCP分组串行发送到第一编码器电路，第一编码器电路被配置为生成作为第一xCP分组和第一时钟信号的函数的编码的第一xCP分组。 第一低电压差分信号（LVDS）电路耦合到第一编码器电路并且被配置为从其串行地接收编码的第一xCP分组。 第一LVDS电路被配置为产生作为编码的第一xCP分组的函数的第一差分信号。
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公开(公告)号：US20100109733A1
公开(公告)日：2010-05-06
申请号：US12622609
申请日：2009-11-20
IPC分类号： H03K3/00
CPC分类号： H03K5/082 , F02D41/20 , F02D41/2403 , H04L12/40006
摘要： An apparatus is disclosed that includes first and second circuits coupled together via a bus, an input pin configured to receive an analog input signal, a digital-to-analog (DAC) convertor configured to convert a multibit reference signal into an analog reference signal, a comparator circuit coupled to the bus, an output of the DAC and to the input pin. The comparator circuit is configured to receive the analog reference signal from the DAC and the analog input signal, and configured to generate a first digital signal set to a first state if the analog reference signal is greater in magnitude than the analog input signal, or set to a second state if analog reference signal is lower in magnitude than the analog input signal. The comparator circuit is also configured to transmit the first digital signal to the first circuit via the bus. The first circuit in turn is configured to receive the first digital signal. In response to receiving the first digital signal, the first circuit is configured to generate a second digital signal set to the first or second state depending on whether the received first digital signal is set to the first or second state. The second circuit is configured to receive the second digital signal from the first circuit via the bus.
摘要翻译： 公开了一种装置，其包括经由总线耦合在一起的第一和第二电路，被配置为接收模拟输入信号的输入引脚，被配置为将多位参考信号转换为模拟参考信号的数模转换器（DAC） 耦合到总线的比较器电路，DAC的输出和输入引脚。 比较器电路被配置为从DAC和模拟输入信号接收模拟参考信号，并且被配置为如果模拟参考信号的幅度大于模拟输入信号，则将第一数字信号设置为第一状态，或者设置 如果模拟参考信号的幅度比模拟输入信号低，则到第二状态。 比较器电路还被配置为经由总线将第一数字信号发送到第一电路。 第一电路又被配置为接收第一数字信号。 响应于接收到第一数字信号，第一电路被配置为根据接收到的第一数字信号是否被设置为第一或第二状态来生成设置为第一或第二状态的第二数字信号。 第二电路被配置为经由总线从第一电路接收第二数字信号。
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公开(公告)号：US08156269B2
公开(公告)日：2012-04-10
申请号：US12756262
申请日：2010-04-08
CPC分类号： H03K5/086 , F02D37/02 , F02D41/008 , F02D41/2435 , F02D41/28
摘要： A system that includes a multiplexer having an output selectively coupled to a plurality of inputs, a bus coupled to the output of the multiplexer, and first and second circuits configured to generate first and second digital signals, respectively. The first digital signal is related to a rotational angle of a crankshaft at a first point in time, and the second digital signal is related to a value of parameter at the first point in time, wherein the parameter is one other than the rotational angle of the crankshaft. The first and second circuits are coupled directly or indirectly to first and second inputs of the multiplexer.
摘要翻译： 一种系统，其包括多路复用器，其具有选择性地耦合到多个输入的输出，耦合到所述多路复用器的输出的总线，以及被配置为分别产生第一和第二数字信号的第一和第二电路。 第一数字信号与第一时间点的曲轴的旋转角度相关，第二数字信号与第一时间点的参数值相关，其中参数是与第一时间点的旋转角度 曲轴。 第一和第二电路直接或间接耦合到多路复用器的第一和第二输入端。
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公开(公告)号：US20100191438A1
公开(公告)日：2010-07-29
申请号：US12756262
申请日：2010-04-08
IPC分类号： G06F19/00
CPC分类号： H03K5/086 , F02D37/02 , F02D41/008 , F02D41/2435 , F02D41/28
摘要： A system that includes a multiplexer having an output selectively coupled to a plurality of inputs, a bus coupled to the output of the multiplexer, and first and second circuits configured to generate first and second digital signals, respectively. The first digital signal is related to a rotational angle of a crankshaft at a first point in time, and the second digital signal is related to a value of parameter at the first point in time, wherein the parameter is one other than the rotational angle of the crankshaft. The first and second circuits are coupled directly or indirectly to first and second inputs of the multiplexer.
摘要翻译： 一种系统，其包括多路复用器，其具有选择性地耦合到多个输入的输出，耦合到所述多路复用器的输出的总线，以及被配置为分别产生第一和第二数字信号的第一和第二电路。 第一数字信号与第一时间点的曲轴的旋转角度相关，第二数字信号与第一时间点的参数值相关，其中参数是与第一时间点的旋转角度 曲轴。 第一和第二电路直接或间接耦合到多路复用器的第一和第二输入端。
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公开(公告)号：US20110090102A1
公开(公告)日：2011-04-21
申请号：US12582757
申请日：2009-10-21
IPC分类号： H03M7/00
CPC分类号： G06F13/4072
摘要： A microprocessor control unit (MCU) is mounted on a printed circuit board. The MCU includes first and second clocked serial interface (CSI) circuits. The first CSI circuit is configured to serially transmit a first xCP packet to a first encoder circuit, which in turn is configured to generate an encoded first xCP packet as a function of the first xCP packet and a first clock signal. A first low voltage differential signal (LVDS) circuit is coupled to the first encoder circuit and configured to serially receive the encoded first xCP packet therefrom. The first LVDS circuit is configured to generate a first differential signal as a function of the encoded first xCP packet.
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公开(公告)号：US08010722B2
公开(公告)日：2011-08-30
申请号：US12622609
申请日：2009-11-20
CPC分类号： H03K5/082 , F02D41/20 , F02D41/2403 , H04L12/40006
摘要： An apparatus is disclosed that includes first and second circuits coupled together via a bus, an input pin configured to receive an analog input signal, a digital-to-analog (DAC) convertor configured to convert a multibit reference signal into an analog reference signal, a comparator circuit coupled to the bus, an output of the DAC and to the input pin. The comparator circuit is configured to receive the analog reference signal from the DAC and the analog input signal, and configured to generate a first digital signal set to a first state if the analog reference signal is greater in magnitude than the analog input signal, or set to a second state if analog reference signal is lower in magnitude than the analog input signal. The comparator circuit is also configured to transmit the first digital signal to the first circuit via the bus. The first circuit in turn is configured to receive the first digital signal. In response to receiving the first digital signal, the first circuit is configured to generate a second digital signal set to the first or second state depending on whether the received first digital signal is set to the first or second state. The second circuit is configured to receive the second digital signal from the first circuit via the bus.
摘要翻译： 公开了一种装置，其包括经由总线耦合在一起的第一和第二电路，被配置为接收模拟输入信号的输入引脚，被配置为将多位参考信号转换为模拟参考信号的数模转换器（DAC） 耦合到总线的比较器电路，DAC的输出和输入引脚。 比较器电路被配置为从DAC和模拟输入信号接收模拟参考信号，并且被配置为如果模拟参考信号的幅度大于模拟输入信号，则将第一数字信号设置为第一状态，或者设置 如果模拟参考信号的幅度比模拟输入信号低，则到第二状态。 比较器电路还被配置为经由总线将第一数字信号发送到第一电路。 第一电路又被配置为接收第一数字信号。 响应于接收到第一数字信号，第一电路被配置为根据接收到的第一数字信号是否被设置为第一或第二状态来生成设置为第一或第二状态的第二数字信号。 第二电路被配置为经由总线从第一电路接收第二数字信号。
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公开(公告)号：US20100114376A1
公开(公告)日：2010-05-06
申请号：US12264538
申请日：2008-11-04
CPC分类号： F02D41/263 , F02D41/20 , F02D41/26 , F02P5/15 , Y02T10/46
摘要： An apparatus and method of scheduling signals. In one embodiment, the method includes a first circuit receiving a first plurality of reference values. The first circuit selects a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory. The first circuit compares the selected reference value to a first match value.
摘要翻译： 一种调度信号的装置和方法。 在一个实施例中，该方法包括接收第一多个参考值的第一电路。 第一电路根据存储在存储器中的第一参考标识符（ID）选择来自第一多个的参考值。 第一电路将所选择的参考值与第一匹配值进行比较。
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公开(公告)号：US08417857B2
公开(公告)日：2013-04-09
申请号：US13418468
申请日：2012-03-13
CPC分类号： F02D41/263 , F02D41/20 , F02D41/26 , F02P5/15 , Y02T10/46
摘要： An apparatus and method of scheduling signals. In one embodiment, the method includes a first circuit receiving a first plurality of reference values. The first circuit selects a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory. The first circuit compares the selected reference value to a first match value.
摘要翻译： 一种调度信号的装置和方法。 在一个实施例中，该方法包括接收第一多个参考值的第一电路。 第一电路根据存储在存储器中的第一参考标识符（ID）选择来自第一多个的参考值。 第一电路将所选择的参考值与第一匹配值进行比较。
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