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公开(公告)号：US07573303B1
公开(公告)日：2009-08-11
申请号：US11781452
申请日：2007-07-23
CPC分类号： H03L7/235 , H03L7/0891 , H03L7/23
摘要： A clock generator includes a clock circuit and a voltage-controlled oscillator in a phase-locked loop. The clock circuit monitors input clock signals and selects one of the input clock signals based on characteristics of the input clock signals. The voltage-controlled oscillator generates a reference clock signal based on the selected clock signal. The clock circuit also includes synthesizers for generating clock signals, each of which has a frequency being a non-integer multiple of a frequency of the reference clock signal. Additionally, the clock circuit individually offsets the clock signals generated by the synthesizers relative to the reference clock signal. The clock generator is capable of switching the input clock signal during operation of the clock generator while maintaining the reference clock signal. Further, the clock generator is programmable to control operation of the clock circuit.
摘要翻译： 时钟发生器包括锁相环中的时钟电路和压控振荡器。 时钟电路监视输入时钟信号，并根据输入时钟信号的特性选择一个输入时钟信号。 压控振荡器基于所选择的时钟信号产生参考时钟信号。 时钟电路还包括用于产生时钟信号的合成器，每个时钟信号的频率是参考时钟信号频率的非整数倍。 此外，时钟电路单独地偏移合成器相对于参考时钟信号产生的时钟信号。 时钟发生器能够在维持参考时钟信号的同时在时钟发生器工作期间切换输入时钟信号。 此外，时钟发生器可编程以控制时钟电路的操作。
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公开(公告)号：US07928773B2
公开(公告)日：2011-04-19
申请号：US12169631
申请日：2008-07-09
IPC分类号： H03B21/00
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/0991
摘要： Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.
摘要翻译： 具有同步相位关系的多个时钟的产生可以在改进其功能，性能，可靠性和故障覆盖的同时降低电路的尺寸，复杂性，功耗，抖动和成本。 多频时钟发生器可以包括用于产生第一时钟和独立DCO的独立数字控制振荡器（DCO），用于产生在共同的多个频率下与第一时钟对准的附加时钟，具有或不具有调整。 独立和依赖的DCO可以通过选择抽头选择信号的序列从延迟锁定环（DLL）生成第一个和附加的时钟。 可以调节分接选择信号以保持第一和另外的时钟的期望的相位和/或频率。 依赖DCO可以基于由独立DCO生成的抽头选择信号的序列来生成抽头选择信号序列，以结合调整，例如PLL误差校正。
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公开(公告)号：US20100007389A1
公开(公告)日：2010-01-14
申请号：US12169631
申请日：2008-07-09
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/0991
摘要： Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.
摘要翻译： 具有同步相位关系的多个时钟的产生可以在改进其功能，性能，可靠性和故障覆盖的同时降低电路的尺寸，复杂性，功耗，抖动和成本。 多频时钟发生器可以包括用于产生第一时钟和独立DCO的独立数字控制振荡器（DCO），用于产生在共同的多个频率下与第一时钟对准的附加时钟，具有或不具有调整。 独立和依赖的DCO可以通过选择抽头选择信号的序列从延迟锁定环（DLL）生成第一个和附加的时钟。 可以调节分接选择信号以保持第一和另外的时钟的期望的相位和/或频率。 依赖DCO可以基于由独立DCO生成的抽头选择信号的序列来生成抽头选择信号序列，以结合调整，例如PLL误差校正。
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