Semiconductor device and method for manufacturing the same
    2.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US07595556B2

    公开(公告)日:2009-09-29

    申请号:US11567681

    申请日:2006-12-06

    Applicant: Jin Ah Kang

    Inventor: Jin Ah Kang

    Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal interconnection, a first interlayer dielectric layer formed on the metal interconnection and having a first contact plug, a second interlayer dielectric layer formed on the first interlayer dielectric layer and having a second contact plug, and a third interlayer dielectric layer formed on the second interlayer dielectric layer and having a third contact plug, wherein the first to third contact plugs are connected to each other.

    Abstract translation: 实施例涉及一种半导体器件及其制造方法。 根据实施例,半导体器件可以包括形成有金属互连的半导体衬底,形成在金属互连上并具有第一接触插塞的第一层间电介质层,形成在第一层间电介质层上的第二层间电介质层, 第二接触插塞和形成在第二层间电介质层上并具有第三接触插塞的第三层间电介质层,其中第一至第三接触插塞彼此连接。

    METHOD OF FORMING A METAL INTERCONNECTION IN A SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FORMING A METAL INTERCONNECTION IN A SEMICONDUCTOR DEVICE 审中-公开
    在半导体器件中形成金属互连的方法

    公开(公告)号:US20070145598A1

    公开(公告)日:2007-06-28

    申请号:US11613751

    申请日:2006-12-20

    Applicant: Jin Ah Kang

    Inventor: Jin Ah Kang

    Abstract: A method includes at least one of: forming a metal interconnection in a semiconductor device; forming an inter-metal dielectric layer over a substrate and/or a lower metal layer; forming a photoresist pattern over an inter-metal dielectric layer; forming a via hole by selectively etching an inter-metal dielectric layer using a photoresist pattern as a mask; forming an ionization layer in a via plug by ion implantation on a sidewall of a via hole; forming a barrier metal layer and a via plug in the via hole; and/or forming a metal interconnection. In embodiments, a barrier metal layer may include titanium nitride and/or a via plug may include tungsten.

    Abstract translation: 一种方法包括以下中的至少一个:在半导体器件中形成金属互连; 在衬底和/或下金属层上形成金属间介电层; 在金属间介电层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为掩模选择性地蚀刻金属间介电层来形成通孔; 在通孔的侧壁上通过离子注入在通孔中形成电离层; 在所述通孔中形成阻挡金属层和通孔塞; 和/或形成金属互连。 在实施例中,阻挡金属层可以包括氮化钛和/或通孔塞可以包括钨。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号:US20070145597A1

    公开(公告)日:2007-06-28

    申请号:US11567681

    申请日:2006-12-06

    Applicant: Jin Ah Kang

    Inventor: Jin Ah Kang

    Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, the semiconductor device may include a semiconductor substrate formed with a metal interconnection, a first interlayer dielectric layer formed on the metal interconnection and having a first contact plug, a second interlayer dielectric layer formed on the first interlayer dielectric layer and having a second contact plug, and a third interlayer dielectric layer formed on the second interlayer dielectric layer and having a third contact plug, wherein the first to third contact plugs are connected to each other.

    Abstract translation: 实施例涉及一种半导体器件及其制造方法。 根据实施例,半导体器件可以包括形成有金属互连的半导体衬底,形成在金属互连上并具有第一接触插塞的第一层间电介质层,形成在第一层间电介质层上的第二层间电介质层, 第二接触插塞和形成在第二层间电介质层上并具有第三接触插塞的第三层间电介质层,其中第一至第三接触插塞彼此连接。

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