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1.发明申请ESD PROTECTION VALIDATOR, AN ESD VALIDATION SYSTEM AND A METHOD OF VALIDATING ESD PROTECTION FOR AN IC 有权ESD保护验证器，ESD验证系统和一种用于对IC进行ESD保护的方法公开(公告)号：US20100169854A1
公开(公告)日：2010-07-01
申请号：US12506597
申请日：2009-07-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L27/0248
摘要： Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.
摘要翻译： 公开了一种静电放电（ESD）保护验证器，一种用于对IC和ESD验证系统进行ESD保护的验证方法。 在一个实施例中，ESD保护验证器包括：（1）电路分析器，被配置为将IC的组件信息与预定义的ESD保护元件进行比较，以识别IC的ESD单元;以及（2）ESD单元验证器，被配置为将相关的物理属性 将所识别的ESD电池与ESD保护要求相结合，并确定其符合性。
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2.发明申请SYSTEM, AN APPARATUS AND A METHOD FOR PERFORMING CHIP-LEVEL ELECTROSTATIC DISCHARGE SIMULATIONS 有权系统，装置和执行芯片级静电放电模拟的方法公开(公告)号：US20100169064A1
公开(公告)日：2010-07-01
申请号：US12434573
申请日：2009-05-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.
摘要翻译： 用于ESD条件下的IC器件的建模器，一种模拟IC ESD ESD模拟系统的ESD方法。 在一个实施例中，建模器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构相比较来提供所识别的ESD单元和IC的电路，以及（2）模型发生器， 基于与所识别的ESD单元和所识别的电路相关联的物理属性，创建所识别的ESD单元和所识别的电路的线性化模型，其中线性化模型的组合表示在ESD条件下IC组件的操作。
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3.发明授权ESD protection validator, an ESD validation system and a method of validating ESD protection for an IC 有权ESD保护验证器，ESD验证系统和验证IC的ESD保护的方法公开(公告)号：US08589839B2
公开(公告)日：2013-11-19
申请号：US12506597
申请日：2009-07-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L27/0248
摘要： Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.
摘要翻译： 公开了一种静电放电（ESD）保护验证器，一种用于对IC和ESD验证系统进行ESD保护的验证方法。 在一个实施例中，ESD保护验证器包括：（1）电路分析器，被配置为将IC的组件信息与预定义的ESD保护元件进行比较，以识别IC的ESD单元;以及（2）ESD单元验证器，被配置为将相关的物理属性 将所识别的ESD电池与ESD保护要求相结合，并确定其符合性。
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公开(公告)号：US07282767B2
公开(公告)日：2007-10-16
申请号：US11155062
申请日：2005-06-17
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/0619
摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well, which touches source junction 512c. Source 512 has further an ohmic (silicided) connection to contact 513. A finger-shaped diode (520) with its cathode (521) is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall (550).
摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有与第一n阱的指状接触（513），其接触源极结512c。 源512还具有与触点513的欧姆（硅化）连接。 具有其阴极（521）的指状二极管（520）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到功率（Vdd）并且大致垂直于第一n阱接触，用作保护壁 （550）。
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公开(公告)号：US07145204B2
公开(公告)日：2006-12-05
申请号：US11107033
申请日：2005-04-15
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/0619
摘要： A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact (513) to the first n-well. Further a finger-shaped diode (520) with its cathode (521) located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well (551) positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall (550).
摘要翻译： 一种用于保护I / O焊盘以防止ESD事件的半导体电路，其包括其源极连接到Vdd和第一n阱的第一n阱（511）中的pMOS晶体管（510），其漏极连接到I / O垫 晶体管具有到第一n阱的手指形状的接触（513）。 此外，指状二极管（520），其阴极（521）位于第二n阱中并连接到I / O焊盘，并且其阳极连接到地。 阳极位于阴极和第一n阱之间，由此指形阳极和阴极定向成大致垂直于指状晶体管n阱接触。 此外，位于第一n阱和二极管之间的第三指状n阱（551），第三n阱连接到地面并且大致垂直于第一n阱接触，用作保护壁（550） 。
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6.发明授权Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system 有权优化IC的ESD保护方法，ESD保护优化器和ESD保护优化系统公开(公告)号：US08176460B2
公开(公告)日：2012-05-08
申请号：US12434578
申请日：2009-05-01
CPC分类号： G06F17/5045 , H01L27/0248
摘要： An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.
摘要翻译： 公开了ESD保护优化器，一种优化IC的ESD保护和ESD保护优化系统的方法。 在一个实施例中，ESD保护优化器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构进行比较来识别IC的ESD单元和电路，以及（2）ESD电阻确定器 被配置为计算与所述电路串联耦合的电阻值，所述电阻值基于与所识别的ESD单元相关联的保护单元物理属性和与所识别的电路相关联的电路物理属性。
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7.发明授权公开(公告)号：US06933741B2
公开(公告)日：2005-08-23
申请号：US10870773
申请日：2004-06-17
CPC分类号： G01R31/002 , G01R31/129 , G01R31/14
摘要： An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off switch relay (403). The relay is resistively connected by a first resistor (402) to the generator and by a second resistor (404) to the socket (405a) for the device-under-test (406); the relay is operable in a partially ionized ambient. A capacitor (407) is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor (410) is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 kΩ and 1 MΩ, preferably about 10 kΩ, several orders of magnitude greater than the on-resistance of the device-under-test.
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8.发明申请METHOD OF OPTIMIZING ESD PROTECTION FOR AN IC, AN ESD PROTECTION OPTIMIZER AND AN ESD PROTECTION OPTIMIZATION SYSTEM 有权优化IC，ESD保护优化器和ESD保护优化系统的ESD保护方法公开(公告)号：US20100169845A1
公开(公告)日：2010-07-01
申请号：US12434578
申请日：2009-05-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H01L27/0248
摘要： An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.
摘要翻译： 公开了ESD保护优化器，一种优化IC的ESD保护和ESD保护优化系统的方法。 在一个实施例中，ESD保护优化器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构进行比较来识别IC的ESD单元和电路，以及（2）ESD电阻确定器 被配置为计算与所述电路串联耦合的电阻值，所述电阻值基于与所识别的ESD单元相关联的保护单元物理属性和与所识别的电路相关联的电路物理属性。
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9.发明授权System, an apparatus and a method for performing chip-level electrostatic discharge simulations 有权用于执行芯片级静电放电模拟的系统，装置和方法公开(公告)号：US08306804B2
公开(公告)日：2012-11-06
申请号：US12434573
申请日：2009-05-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.
摘要翻译： 用于ESD条件下的IC器件的建模器，一种模拟IC ESD ESD模拟系统的ESD方法。 在一个实施例中，建模器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构相比较来提供所识别的ESD单元和IC的电路，以及（2）模型发生器， 基于与所识别的ESD单元和所识别的电路相关联的物理属性，创建所识别的ESD单元和所识别的电路的线性化模型，其中线性化模型的组合表示在ESD条件下IC组件的操作。
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