公开(公告)号：US6112273A

公开(公告)日：2000-08-29

申请号：US719599

申请日：1996-09-25

申请人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

发明人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

IPC分类号： G06F13/24 ,  G06F9/18

CPC分类号： G06F13/24

摘要： An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

摘要翻译： 电子系统（100）包括具有卡系统管理中断（SMI）输出引脚（CRDSMI＃）和中断引脚（IRQ3-5）的第一集成电路（IC）（112）和逻辑电路（1620,1630） 具有连接到卡SMI引脚的输出。 该逻辑电路还具有分别连接到用于第一和第二卡（CARD A，B）的第一和第二组寄存器和逻辑的输入。 第一和第二组寄存器和逻辑中的每一个包括分别由至少卡事件（CDCHG）和电池条件事件（BWARN）设置位的第一寄存器（CSC REG）。 逻辑门（2672）响应于组合来自第一寄存器的位。 第二个寄存器（INT AND GEN CTRL REG）具有一个位（SMIEN），用于根据位的状态（SMIEN）指导逻辑门（2672）的输出用于普通中断或用于系统管理中断。 第二集成电路（110）具有系统管理中断（SMI＃）输出引脚和SMI电路（2370），其包括连接到包括第一集成电路的卡SMI输出的符合SMI响应的事件源的SMI寄存器（2610）。 该第二IC（110）还具有连接到SMI寄存器（2610）的掩模SMI寄存器（2620），以选择SMI响应的特定事件源。 逻辑电路（2634,2638）由SMI寄存器（2610）馈送，用于组合所选择的事件源以提供内部SMI输出（SMIOUT）。 还公开了其它电路，系统和方法。

公开(公告)号：US5684997A

公开(公告)日：1997-11-04

申请号：US718136

申请日：1996-09-18

申请人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

发明人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

IPC分类号： G06F13/24 ,  G06F9/18 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

摘要翻译： 电子系统（100）包括具有卡系统管理中断（SMI）输出引脚（CRDSMI＃）和中断引脚（IRQ3-5）的第一集成电路（IC）（112）和逻辑电路（1620,1630） 具有连接到卡SMI引脚的输出。 该逻辑电路还具有分别连接到用于第一和第二卡（CARD A，B）的第一和第二组寄存器和逻辑的输入。 第一和第二组寄存器和逻辑中的每一个包括分别由至少卡事件（CDCHG）和电池条件事件（BWARN）设置位的第一寄存器（CSC REG）。 逻辑门（2672）响应于组合来自第一寄存器的位。 第二个寄存器（INT AND GEN CTRL REG）具有一个位（SMIEN），用于根据位的状态（SMIEN）指导逻辑门（2672）的输出用于普通中断或用于系统管理中断。 第二集成电路（110）具有系统管理中断（SMI＃）输出引脚和SMI电路（2370），其包括连接到包括第一集成电路的卡SMI输出的符合SMI响应的事件源的SMI寄存器（2610）。 该第二IC（110）还具有连接到SMI寄存器（2610）的掩模SMI寄存器（2620），以选择SMI响应的特定事件源。 逻辑电路（2634,2638）由SMI寄存器（2610）馈送，用于组合所选择的事件源以提供内部SMI输出（SMIOUT）。 还公开了其它电路，系统和方法。

公开(公告)号：US06421754B1

公开(公告)日：2002-07-16

申请号：US08480179

申请日：1995-06-07

申请人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

发明人： Weiyuen Kau ,  John H. Cornish ,  Qadeer A. Qureshi ,  Shannon A. Wichman

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

摘要翻译： 电子系统（100）包括具有卡系统管理中断（SMI）输出引脚（CRDSMI＃）和中断引脚（IRQ3-5）的第一集成电路（IC）（112）和逻辑电路（1620,1630） 具有连接到卡SMI引脚的输出。 该逻辑电路还具有分别连接到用于第一和第二卡（CARD A，B）的第一和第二组寄存器和逻辑的输入。 第一和第二组寄存器和逻辑中的每一个包括分别由至少卡事件（CDCHG）和电池条件事件（BWARN）设置位的第一寄存器（CSC REG）。 逻辑门（2672）响应于组合来自第一寄存器的位。 第二个寄存器（INT AND GEN CTRL REG）具有一个位（SMIEN），用于根据位的状态（SMIEN）指导逻辑门（2672）的输出用于普通中断或用于系统管理中断。 第二集成电路（110）具有系统管理中断（SMI＃）输出引脚和SMI电路（2370），其包括连接到包括第一集成电路的卡SMI输出的符合SMI响应的事件源的SMI寄存器（2610）。 该第二IC（110）还具有连接到SMI寄存器（2610）的掩模SMI寄存器（2620），以选择SMI响应的特定事件源。 逻辑电路（2634,2638）由SMI寄存器（2610）馈送，用于组合所选择的事件源以提供内部SMI输出（SMIOUT）。 还公开了其它电路，系统和方法。

公开(公告)号：US5943507A

公开(公告)日：1999-08-24

申请号：US915154

申请日：1997-08-20

申请人： John H. Cornish ,  Shannon A. Wichman ,  Qadeer A. Qureshi

发明人： John H. Cornish ,  Shannon A. Wichman ,  Qadeer A. Qureshi

IPC分类号： G06F13/24 ,  G06F13/00

CPC分类号： G06F13/24

摘要： A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ("MPU" 102), a peripheral processing unit ("PPU" 110) that communicates with the MPU and a peripheral control unit ("PCU" 112) capable of communicating with the PPU and with at least one associated peripheral device. The PCU has associated therewith a first number, m, of interrupts for signalling to the MPU. The MPU has a second number, n, of interrupt channels over which interrupts are communicable to said MPU. A first register (IN1616) is provided in the PCU for storing a routing value representing the assignment of the m interrupts of the PCU to a selected subset of m channels of the n interrupt channels. A second register (IN1222) is provided in the PPU for storing the routing value. A number, m, connections are provided between the PCU and the PPU for transmitting the m interrupts from the PCU to the PPU. Finally, a logic unit (3820, 3830, 914) is provided that is responsive to the receipt of an interrupt on one of the m connections and to the stored routing value in the second register for communicating an interrupt to the MPU and for identifying to the MPU the m selected interrupt channels to which the communicated interrupt is assigned. Other devices, systems and methods are also disclosed.

摘要翻译： 一种计算机系统，包括用于可编程地将中断分配给更大的一组中断信道的装置。 计算机系统包括微处理单元（“MPU”102），与MPU通信的外围处理单元（“PPU”110）和能够与PPU进行通信的外围控制单元（“PCU”112） 一个相关的外围设备。 PCU与其相关联地具有用于向MPU发信号的中断的第一数量m。 MPU具有第二数量的n个中断通道，中断可以通过该中断通道传送到所述MPU。 在PCU中提供第一寄存器（IN1616），用于将表示PCU的m个中断的分配的路由值存储到n个中断信道的选定的m个信道的子集中。 PPU中提供了第二个寄存器（IN1222），用于存储路由值。 在PCU和PPU之间提供数字m连接，用于将m个中断从PCU发送到PPU。 最后，提供逻辑单元（3820,3830,914），其响应于在m个连接中的一个上接收到中断以及第二寄存器中存储的路由值，以将中断传送给MPU，并且用于识别 MPU分配了通信中断的m个选择的中断通道。 还公开了其他装置，系统和方法。