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公开(公告)号：US07616509B2
公开(公告)日：2009-11-10
申请号：US11777635
申请日：2007-07-13
申请人： Qadeer A. Qureshi , Sushama Davar , Thomas Jew
发明人： Qadeer A. Qureshi , Sushama Davar , Thomas Jew
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.
摘要翻译： 在存储器的操作期间动态地调整集成电路上的存储器的电源电压。 存储器的操作包括以电源电压供电存储器。 在操作存储器的同时，集成电路的测试存储器同时供电。 测试存储器和存储器各自包括第一位单元配置类型的位单元。 基于测试存储器的测试，在操作存储器的同时调整电源电压的电压电平。 电压电平通过外部变化进行调整，以保证不会使存储器发生故障的值，同时也可以精确地最小化电源电压。 系统和方法可以用任何类型的存储器来实现。 存储器和测试存储器可以物理地实现为分离或散布在集成电路上。
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2.发明授权Method and system for improved memory access in accelerated graphics port systems 失效加速图形端口系统中改进内存访问的方法和系统公开(公告)号：US06559850B1
公开(公告)日：2003-05-06
申请号：US09183205
申请日：1998-10-30
IPC分类号： G06F1314
CPC分类号： G06F13/1626 , G09G5/363 , G09G5/39
摘要： A method and system for improving memory access in Accelerated Graphics Port systems. The method and system associate a transaction id with individual data transactions within a number of Accelerated Graphics Port (AGP) pipelined data transactions, and identify the individual data transactions within the number of AGP pipelined data transactions via the transaction id. In one instance, the association of a transaction id with individual data transactions includes but is not limited to associating a transaction id with each individual memory read request within a number of AGP pipelined memory read requests and associating an identical transaction id with each individual data unit, within a number of pipelined data units, corresponding to each individual memory read request within the number of AGP pipelined memory requests. In another instance, the association of a transaction id with individual memory read requests within a number of AGP pipelined memory read requests includes but is not limited to placing a transaction id on a Side Band Addressing bus substantially immediately after placing a read request on the same Side Band Addressing bus, and the association of an identical transaction id with individual data units within a number of the data units associated with pipelined data units corresponding to each of the AGP pipelined memory read requests includes but is not limited to placing a transaction id on a ST[2::0] bus while substantially simultaneously placing a data unit on an AGP Interconnect.
摘要翻译： 一种用于改进加速图形端口系统中的存储器访问的方法和系统。 该方法和系统将事务ID与多个加速图形端口（AGP）流水线数据事务中的各个数据事务相关联，并通过事务标识识别AGP流水线数据事务数量内的各个数据事务。 在一个实例中，事务id与各个数据事务的关联包括但不限于在多个AGP流水线存储器读取请求中将事务ID与每个单独的存储器读取请求相关联，并且将相同的事务ID与每个单独的数据单元相关联 在多个流水线数据单元内，对应于AGP流水线存储器请求数量内的每个单独的存储器读取请求。 在另一个实例中，事务ID与多个AGP流水线存储器读取请求中的各个存储器读取请求的关联包括但不限于在将读取请求放在同一边缘上之后立即在边带寻址总线上放置事务ID 边带寻址总线，以及与相应于每个AGP流水线存储器读取请求的流水线数据单元相关联的数量的数据单元中的相同事务ID与各个数据单元的关联包括但不限于将事务ID放在 ST [2 :: 0]总线，同时将数据单元同时放置在AGP互连上。
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公开(公告)号：US06421754B1
公开(公告)日：2002-07-16
申请号：US08480179
申请日：1995-06-07
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.
摘要翻译： 电子系统（100）包括具有卡系统管理中断（SMI）输出引脚（CRDSMI＃）和中断引脚（IRQ3-5）的第一集成电路（IC）（112）和逻辑电路（1620,1630） 具有连接到卡SMI引脚的输出。 该逻辑电路还具有分别连接到用于第一和第二卡（CARD A，B）的第一和第二组寄存器和逻辑的输入。 第一和第二组寄存器和逻辑中的每一个包括分别由至少卡事件（CDCHG）和电池条件事件（BWARN）设置位的第一寄存器（CSC REG）。 逻辑门（2672）响应于组合来自第一寄存器的位。 第二个寄存器（INT AND GEN CTRL REG）具有一个位（SMIEN），用于根据位的状态（SMIEN）指导逻辑门（2672）的输出用于普通中断或用于系统管理中断。 第二集成电路（110）具有系统管理中断（SMI＃）输出引脚和SMI电路（2370），其包括连接到包括第一集成电路的卡SMI输出的符合SMI响应的事件源的SMI寄存器（2610）。 该第二IC（110）还具有连接到SMI寄存器（2610）的掩模SMI寄存器（2620），以选择SMI响应的特定事件源。 逻辑电路（2634,2638）由SMI寄存器（2610）馈送，用于组合所选择的事件源以提供内部SMI输出（SMIOUT）。 还公开了其它电路，系统和方法。
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4.发明授权Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority 失效基于中断优先级将中断源信息存储在中断控制器中的装置和方法
公开(公告)号：US5905898A
公开(公告)日：1999-05-18
申请号：US605873
申请日：1996-02-23
申请人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
发明人： Qadeer A. Qureshi , Dan S. Mudgett , James R. MacDonald , Douglas D. Gephardt , Rodney W. Schmidt
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
摘要翻译： 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 中断请求识别码分配给每个中断请求并存储在嵌套缓冲区中。 用于引用中断请求的中断请求标识代码按其优先顺序存储。 每个嵌套缓冲区只需要等于优先级数量的条目数。
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5.发明授权System and method for referencing interrupt request information in a programmable interrupt controller 失效用于在可编程中断控制器中引用中断请求信息的系统和方法
公开(公告)号：US5850558A
公开(公告)日：1998-12-15
申请号：US575664
申请日：1995-12-19
CPC分类号： G06F13/24
摘要： A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.
摘要翻译： 提供可编程中断控制器，用于包括一个或多个CPU的计算机系统。 可编程中断控制器包括中断请求接口，存储设备以及具有中断嵌套缓冲器的至少一个处理器接口。 每个中断请求都分配唯一的中断识别码，用于引用与每个中断请求相关联的存储设备中的信息。 中断请求接口使用唯一的中断标识码来访问每个中断请求的信息，并确定中断请求是否应继续到其中一个处理器接口。 处理器接口使用唯一的中断识别码来访问信息，以确定中断请求是否和何时发送给其中一个CPU。
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6.发明授权
公开(公告)号：US5850555A
公开(公告)日：1998-12-15
申请号：US575683
申请日：1995-12-19
CPC分类号： G06F13/24
摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.
摘要翻译： 提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。 可编程中断控制器包括中断请求接口，有效性检查器和至少一个处理器接口。 有效性检查器通过中断控制器来处理每个中断请求的状态。 如果中断请求无效，则中断请求被取消。 或者，如果中断请求在CPU响应后变为无效，则可编程中断控制器发出伪中断向量。
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公开(公告)号：US5712991A
公开(公告)日：1998-01-27
申请号：US374357
申请日：1995-01-18
CPC分类号： G06F3/061 , G06F13/4059 , G06F3/0656 , G06F3/0674
摘要： A peripheral controller device (14) controlling at least a first peripheral device (16) attached thereto, the controller device including a programmable and selectable buffer memory for utilization with a first type and a second type of write instruction for writing data to first type (24) and a second type (26), respectively, of memory in the peripheral device (16). The peripheral controller device includes an n deep buffer memory (36), where n is an integer greater than one, for buffering the write instructions. A user may programmably indicate whether only the first type of write instruction is to be buffered or both types of instructions are to be buffered. Responsive to such programming, write instructions are examined to determine if they are of the first type or the second type. Depending on the programming, write instructions of the second type are routed to the buffer or are routed by bypassing the buffer memory.
摘要翻译： 控制至少第一外围设备（16）附连到其上的外围控制器设备（14），所述控制器设备包括用于将数据写入第一类型的第一类型和第二类型写入指令的可编程和可选择的缓冲存储器 24）和外围设备（16）中的存储器的第二类型（26）。 外围控制器装置包括n个深缓冲存储器（36），其中n是大于1的整数，用于缓冲写入指令。 用户可以可编程地指示是否要缓冲第一类写入指令或者两种类型的指令都被缓冲。 响应于这种编程，检查写入指令以确定它们是第一类型还是第二类型。 根据编程，第二种类型的写入指令被路由到缓冲区，或通过绕过缓冲存储器进行路由。
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8.发明授权Fail-safe method to read a timer which is based on a particular clock with another asynchronous circit 失效使用另一个异步循环读取基于特定时钟的定时器的故障安全方法
公开(公告)号：US5703919A
公开(公告)日：1997-12-30
申请号：US633671
申请日：1996-04-17
CPC分类号： G04G5/00
摘要： A method and apparatus for reading a timer with an asynchronous circuit. A computer system is provided having a system clock and an asynchronous timer clock. The computer system includes a counter clocking from the timer clock and a latch coupled to output of the counter. First logic, synchronized to the timer clock, is coupled to control the latch responsive to a control signal from the computer system. Second logic synchronized to the system clock and coupled to the first logic is configured to provide an indication to the computer system of when the system can read the latched data and be assured of its validity. The computer system will thereby be prevented from reading the timer before it has stabilized.
摘要翻译： 一种用异步电路读取定时器的方法和装置。 提供了具有系统时钟和异步定时器时钟的计算机系统。 计算机系统包括来自定时器时钟的计时器和耦合到计数器的输出的锁存器。 与定时器时钟同步的第一逻辑被耦合以响应于来自计算机系统的控制信号来控制锁存器。 与系统时钟同步并耦合到第一逻辑的第二逻辑被配置为向计算机系统提供系统何时读取锁存的数据并确保其有效性的指示。 因此，计算机系统在其稳定之前将被阻止读取定时器。
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公开(公告)号：US5630108A
公开(公告)日：1997-05-13
申请号：US375317
申请日：1995-01-18
CPC分类号： G06F13/4217
摘要： A bus interface timing unit responsive to a system clock signal having a frequency that is selectable among a plurality of frequencies. The bus interface timing unit provides timing signals to a bus interface unit that performs functions involving control signals having predetermined timing requirements, such timing requirements being substantially independent of the frequency of the system clock signal. The bus interface timing unit includes a signal generator (20) which is responsive to the system clock signal, and which generates the control signals. These control signals include at least one event signal controlling a time duration in which a predetermined event occurs. Also included is a control unit (10), responsive to a signal representative of the selected frequency of the system clock signal, that controls the signal generator such that the event signal timing is generated in accordance with the predetermined requirements the selected frequencies.
摘要翻译： 总线接口定时单元，其响应于具有可在多个频率中选择的频率的系统时钟信号。 总线接口定时单元向总线接口单元提供定时信号，总线接口单元执行涉及具有预定定时要求的控制信号的功能，这种定时要求基本上与系统时钟信号的频率无关。 总线接口定时单元包括响应于系统时钟信号并产生控制信号的信号发生器（20）。 这些控制信号包括控制发生预定事件的持续时间的至少一个事件信号。 还包括控制单元（10），其响应于表示系统时钟信号的选定频率的信号，其控制信号发生器，使得根据所选频率的预定要求生成事件信号定时。
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公开(公告)号：US09384856B2
公开(公告)日：2016-07-05
申请号：US14102727
申请日：2013-12-11
IPC分类号： G11C29/00 , G11C29/38 , G06F11/263 , G11C29/42 , G11C29/44
CPC分类号： G11C29/38 , G06F11/263 , G11C29/42 , G11C29/44 , G11C2029/4402
摘要： A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.
摘要翻译： 存储器系统包括存储器和耦合到存储器的内置自检（BIST）单元。 BIST单元被配置为在存储器上运行测试模式以累积故障签名，并且基于存储器中的多个位置处的累积故障签名来存储故障签名信息。
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