公开(公告)号：US09117022B1

公开(公告)日：2015-08-25

申请号：US13352090

申请日：2012-01-17

申请人： Gordon Raymond Chiu ,  John Stuart Freeman

发明人： Gordon Raymond Chiu ,  John Stuart Freeman

IPC分类号： G06F13/36 ,  G06F13/364

CPC分类号： G06F13/364

摘要： Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.

摘要翻译： 提供了用于提高集成电路（IC）中仲裁逻辑的速度和减小面积的系统和方法。 例如，在一个实施例中，一种方法包括在第一级仲裁块中仲裁至少一个主请求。 第二级仲裁块从第一级仲裁至少两个仲裁块。 第一级复用器至少部分地基于第一级仲裁块的仲裁来复用至少一个主有效载荷。 第二级复用器复用从第一级复用器传播的至少两个信号。

公开(公告)号：US08201114B1

公开(公告)日：2012-06-12

申请号：US12590933

申请日：2009-11-17

申请人： Valavan Manohararajah ,  Gordon Raymond Chiu ,  John Stuart Freeman

发明人： Valavan Manohararajah ,  Gordon Raymond Chiu ,  John Stuart Freeman

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054

摘要： A method for optimizing a system on a target device is disclosed. A LUT is unpacked to form a plurality of LUTs of a smaller size upon determining that the unpacking can satisfy one or more predefined objectives. The plurality of LUTs are repacked such that the design for the system is improved. Other embodiments are disclosed.

摘要翻译： 公开了一种用于优化目标设备上的系统的方法。 在确定拆包可以满足一个或多个预定义目标的情况下，LUT被解包以形成较小尺寸的多个LUT。 多个LUT被重新包装，使得系统的设计得到改进。 公开了其他实施例。

公开(公告)号：US10599404B1

公开(公告)日：2020-03-24

申请号：US13486151

申请日：2012-06-01

申请人： David Neto ,  Deshanand Singh ,  Tomasz Czajkowski ,  John Stuart Freeman ,  Tian Yi David Han

发明人： David Neto ,  Deshanand Singh ,  Tomasz Czajkowski ,  John Stuart Freeman ,  Tian Yi David Han

IPC分类号： G06F9/45 ,  G06F8/41 ,  G06F8/40

摘要： A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.