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    Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
    1.
    发明授权
    Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays 有权
    用于对现场可编程门阵列执行放置后功能分解的方法和装置

    公开(公告)号：US07290239B1

    公开(公告)日：2007-10-30

    申请号：US10858300

    申请日：2004-06-01

    申请人： Deshanand Singh ,  Valavan Manohararajah ,  Karl Schabas

    发明人： Deshanand Singh ,  Valavan Manohararajah ,  Karl Schabas

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes synthesizing a design for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. The design for the system is restructured after placement locations for the components are determined to improve timing for the system.

    摘要翻译： 利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括合成系统的设计。 设计中的组件映射到目标设备上的资源。 确定目标设备上的组件的位置位置。 系统的设计在重新组建了组件的放置位置后才能改进系统的时序。

    INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS
    2.
    发明申请
    INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS 有权
    具有多级逻辑区域的集成电路

    公开(公告)号：US20130257476A1

    公开(公告)日：2013-10-03

    申请号：US13434847

    申请日：2012-03-29

    申请人： David Cashman ,  David Lewis ,  Valavan Manohararajah

    发明人： David Cashman ,  David Lewis ,  Valavan Manohararajah

    IPC分类号： H03K19/20

    CPC分类号： H03K19/17728

    摘要： A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.

    摘要翻译： 可编程集成电路上的可编程逻辑区域可以包括接收可编程逻辑区域输入信号的第一组查询表和产生可编程逻辑区域输出信号的第二组查找表。 多路复用器电路可以插入在第一组和第二组查找表之间。 多路复用器电路可以与来自第一组查找表的输出信号并行地接收可编程逻辑区域输入信号，并且可以向第二组查找表提供相应的所选择的信号。 可编程逻辑区域输入信号可以由第一组和第二组查找表共享。 逻辑电路可以耦合到第一组和第二组查找表的输出。 逻辑电路可以被配置为逻辑地组合来自第一组和第二组查找表的输出信号。

    Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
    5.
    发明授权
    Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
    将任意逻辑功能映射到同步嵌入式存储器中的系统和方法

    公开(公告)号：US07444613B1

    公开(公告)日：2008-10-28

    申请号：US11408762

    申请日：2006-04-21

    申请人： Gordon Chiu ,  Deshanand Singh ,  Valavan Manohararajah ,  Stephen Brown

    发明人： Gordon Chiu ,  Deshanand Singh ,  Valavan Manohararajah ,  Stephen Brown

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.

    摘要翻译： 提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。 这种技术增加了可以适应PLD的逻辑量。 如果区域节省很大，则可以选择较小的PLD来实现特定的电路。 本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。 在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。 本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。

    Method and system for operating a circuit
    6.
    发明授权
    Method and system for operating a circuit 有权
    操作电路的方法和系统

    公开(公告)号：US08847624B1

    公开(公告)日：2014-09-30

    申请号：US13358449

    申请日：2012-01-25

    申请人： Valavan Manohararajah

    发明人： Valavan Manohararajah

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/17728

    摘要： Operation of a programmable circuit is described. A circuit including a plurality of multiplexers may be used to perform at least one operation on a plurality of signals. The at least one operation may be performed by the multiplexers using a select line coupled to or shared by the multiplexers. Each input of the circuit may couple to a respective output of a plurality of logic elements. As such, the circuit may be used to perform at least one operation on signals supplied from a plurality of logic elements, thereby expanding the functionality of at least one logic element coupled to the circuit and/or increasing the number of logic elements and other resources available for implementing user designs or performing other functions.

    摘要翻译： 描述可编程电路的操作。 可以使用包括多个多路复用器的电路来对多个信号执行至少一个操作。 所述至少一个操作可以由多路复用器使用耦合到或由多路复用器共享的选择线来执行。 电路的每个输入可以耦合到多个逻辑元件的相应输出。 这样，电路可以用于对从多个逻辑元件提供的信号执行至少一个操作，从而扩展耦合到电路的至少一个逻辑元件的功能和/或增加逻辑元件和其他资源的数量 可用于实现用户设计或执行其他功能。

    Method and apparatus for performing asynchronous and synchronous reset removal during synthesis
    7.
    发明申请
    Method and apparatus for performing asynchronous and synchronous reset removal during synthesis 有权
    在合成期间执行异步和同步复位去除的方法和装置

    公开(公告)号：US20110283250A1

    公开(公告)日：2011-11-17

    申请号：US12800227

    申请日：2010-05-11

    申请人： Valavan Manohararajah

    发明人： Valavan Manohararajah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed.

    摘要翻译： 公开了一种在目标设备上设计系统的方法。 通过将系统的高级描述转换为门，寄存器和复位电路来合成系统。 执行分析以识别和去除冗余复位电路。 在冗余复位电路被去除后，系统进行了优化。 公开了其他实施例。

    Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
    9.
    发明授权
    Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
    将任意逻辑功能映射到同步嵌入式存储器中的系统和方法

    公开(公告)号：US07797666B1

    公开(公告)日：2010-09-14

    申请号：US12244635

    申请日：2008-10-02

    申请人： Gordon Chiu ,  Deshanand Singh ,  Valavan Manohararajah ,  Stephen Brown

    发明人： Gordon Chiu ,  Deshanand Singh ,  Valavan Manohararajah ,  Stephen Brown

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.

    摘要翻译： 提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。 这种技术增加了可以适应PLD的逻辑量。 如果区域节省很大，则可以选择较小的PLD来实现特定的电路。 本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。 在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。 本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。