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公开(公告)号:US5961653A
公开(公告)日:1999-10-05
申请号:US803053
申请日:1997-02-19
申请人: Howard Leo Kalter , John Edward Barth, Jr. , Jeffrey Harris Dreibelbis , Rex Ngo Kho , John Stuart Parenteau, Jr. , Donald Lawrence Wheater , Yotaro Mori
发明人: Howard Leo Kalter , John Edward Barth, Jr. , Jeffrey Harris Dreibelbis , Rex Ngo Kho , John Stuart Parenteau, Jr. , Donald Lawrence Wheater , Yotaro Mori
CPC分类号: G06F11/2635 , G11C29/12 , G11C29/32
摘要: An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.
摘要翻译: 具有嵌入在逻辑中的DRAM的集成芯片通过原位处理器定向的BIST宏进行测试。 BIST提供两个ROMS,一个用于存储测试指令,另一个用于存储测试指令,第二个可扫描,为存储在第一个ROM中的测试指令提供顺序,以及分支和循环功能。 此外,BIST宏还具有用于监视DRAM内的故障并用于替换失败的字和/或数据线的冗余分配逻辑部分。 通过将DRAM以0.5mb的增量叠加到4.0mb的最大值或以1.0mb的增量最大为8mb的最大值,所有这些都由BIST宏控制和测试,具有高度粒度的定制芯片设计可以是 实现并针对更大的ASIC中的特定应用量身定做。