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1.发明授权
公开(公告)号：US4227185A
公开(公告)日：1980-10-07
申请号：US964774
申请日：1978-11-29
申请人： John W. Kronlage
发明人： John W. Kronlage
CPC分类号： H03M1/1028 , G01K1/028 , H03M1/1061 , H03M1/52
摘要： A novel analog-to-digital converter is integrated on a semiconductor substrate utilizing I.sup.2 L techniques. The resulting converter, which utilizes dual slope integration to generate a digital signal, operates from a single low-voltage power supply and has few external components. The converter is suitable for integration with I.sup.2 L digital circuitry to provide a complete digital system, which operates in accordance with an analog input signal, on a single semiconductor chip.
摘要翻译： 利用I2L技术在半导体衬底上集成了一个新颖的模拟 - 数字转换器。 所得到的转换器利用双斜率积分来产生数字信号，从单个低压电源运行，并且具有很少的外部元件。 该转换器适用于与I2L数字电路集成，以在单个半导体芯片上提供完全符合模拟输入信号的数字系统。
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公开(公告)号：US4079338A
公开(公告)日：1978-03-14
申请号：US743993
申请日：1976-11-22
申请人： John W. Kronlage
发明人： John W. Kronlage
CPC分类号： G01K1/028 , H03K3/0315 , H03K5/15093
摘要： A novel I.sup.2 L ring oscillator circuit includes means by which the repetition rate is adjustable. A plurality of cascaded logic gate stages are coupled in a ring configuration to achieve a plurality of astable states. Frequency adjustments are made by varying the amount of injection current applied to the logic gates which comprise the ring oscillator. Lowering injection current increases delay time from one astable state to the next resulting in a lower frequency repetition rate. The ring oscillator may be fabricated on a single substrate along with other I.sup.2 L circuitry and be utilized as the clock source therefore. In one embodiment of the circuit, a plurality of discrete frequency adjustments are provided; by selection of a particular lead pattern during fabrication of the oscillator, the appropriate injection current to the oscillator logic gates is provided.
摘要翻译： 一个新颖的I2L环形振荡器电路包括重复率可调的装置。 多个级联逻辑门级以环形配置耦合以实现多个不稳定状态。 通过改变施加到包括环形振荡器的逻辑门的注入电流的量来进行频率调整。 降低注入电流增加了从一个不稳定状态到下一个状态的延迟时间，导致较低的频率重复率。 环形振荡器可以与其他I2L电路一起制造在单个衬底上，因此可用作时钟源。 在电路的一个实施例中，提供多个离散频率调整; 通过在制造振荡器期间选择特定的引线图案，提供了到振荡器逻辑门的适当注入电流。
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公开(公告)号：US4835738A
公开(公告)日：1989-05-30
申请号：US846673
申请日：1986-03-31
IPC分类号： G06F9/22
CPC分类号： G06F9/22
摘要： A microsequencer includes a memory array (110) which is interfaced with a push/pop register (100). Data is input to the push/pop register (100) through a multiplexer (104) and also to Read register (102). The stack comprised of the RAM (110) and the register (100) can be push or pop with control logic (120). Stack pointer (130) and Read pointer (134) are provided for storing the stack and read pointers. The Read register (102) allows reading of data independent of the contents of the push/pop register (100) and the Read pointer (134) allows independent reading of information in the RAM (110).
摘要翻译： 微定序器包括与推/放寄存器（100）接口的存储器阵列（110）。 数据通过多路复用器（104）和读寄存器（102）输入到推/弹寄存器（100）。 由RAM（110）和寄存器（100）组成的堆叠可以通过控制逻辑（120）进行推送或弹出。 堆栈指针（130）和读指针（134）用于存储堆栈和读指针。 读寄存器（102）允许独立于推/弹寄存器（100）的内容读取数据，并且读指针（134）允许RAM（110）中的信息的独立读取。
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公开(公告)号：US4809211A
公开(公告)日：1989-02-28
申请号：US912013
申请日：1986-09-25
申请人： John W. Kronlage
发明人： John W. Kronlage
CPC分类号： G06F7/5324 , G06F2207/3884 , G06F7/5338
摘要： An n.times.n bit multiplier of a type having input and output registers and associated multiplexers, a multiplier array and adders, a shifter and an accumulator. The multiplier includes a temporary register having an input coupled in parallel with an input of the accumulator to an output of the shifter and an output coupled to a multiplexer for controlling the flow of output data from the temporary register to the multiplier array. The temporary register is responsive to a SELREG control signal to become enabled and disabled. An input of the shifter is coupled to an output of the adder.
摘要翻译： 具有输入和输出寄存器和相关多路复用器的类型的nxn位乘法器，乘法器阵列和加法器，移位器和累加器。 乘法器包括具有与累加器的输入并联耦合到移位器的输出的输入的暂时寄存器，以及耦合到多路复用器的输出，用于控制从临时寄存器到乘法器阵列的输出数据的流动。 临时寄存器响应SELREG控制信号变为使能和禁止。 移位器的输入端耦合到加法器的输出端。
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5.发明授权
公开(公告)号：US4107667A
公开(公告)日：1978-08-15
申请号：US743900
申请日：1976-11-22
申请人： John W. Kronlage
发明人： John W. Kronlage
摘要： In a dual slope analog-to-digital converter, the conversion cycle is divided into three states; a first state in which the system is initialized by discharging an integration capacitor, a second state in which integration is performed with an analog voltage representing the measured parameter and a third state in which integration is performed with an analog reference voltage representing the full scale of the measured parameter. The duration of each state, derived from a counter, is selected according to the particular application in which the analog-to-digital converter is utilized. In one embodiment, each count is representative of a unit of the parameter being measured or a fraction thereof. The count or value which represents the commencement of the third state has a selected relationship to the minimum value of the measured parameter best suited for the particular application. The number of counts in the second state is selected to be equal to or a multiple of the desired full scale range of the parameter to be measured.
摘要翻译： 在双斜率模数转换器中，转换周期分为三种状态： 第一状态，其中通过放电积分电容器来初始化系统;第二状态，其中以表示测量参数的模拟电压进行积分;以及第三状态，其中，以表示所述测量参数的模拟参考电压执行积分， 测量参数。 根据使用模数转换器的具体应用，选择从计数器导出的每个状态的持续时间。 在一个实施例中，每个计数代表正在测量的参数的单位或其分数。 表示第三状态的开始的计数或值与最适合特定应用的测量参数的最小值具有选择的关系。 第二状态下的计数选择为要测量的参数的期望满量程范围的倍数。
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