利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.013 秒)

    Programmable logic unit and method for translating and processing instructions using interpretation registers
    2.
    发明授权
    Programmable logic unit and method for translating and processing instructions using interpretation registers 有权
    可编程逻辑单元和使用解释寄存器翻译和处理指令的方法

    公开(公告)号：US08572354B2

    公开(公告)日：2013-10-29

    申请号：US11536483

    申请日：2006-09-28

    申请人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    发明人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/3013 ,  G06F9/30178 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3822

    摘要： An architecture for microprocessors, in which instructions include a type identifier, selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).

    摘要翻译： 用于微处理器的架构，其中指令包括类型标识符，选择若干解释寄存器之一。 解释寄存器保存用于解释每个指令的操作码的信息，使得压缩指令流（具有类型标识符）可以被转换成扩展指令流。 优选地，类型标识符还将定序器指令与处理单元指令区分开，并且甚至可以区分不同类型的定序器指令（以及不同类型的处理单元指令）。

    Flexible Microprocessor Register File
    4.
    发明申请
    Flexible Microprocessor Register File 审中-公开
    灵活的微处理器寄存器文件

    公开(公告)号：US20120042135A1

    公开(公告)日：2012-02-16

    申请号：US12916431

    申请日：2010-10-29

    申请人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    发明人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30098 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/30141

    摘要： Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

    摘要翻译： 在寄存器文件中以多种格式查看数据的体系结构和方法。 各种公开的实施例允许一个寄存器文件内的多个连续寄存器看起来被一个指令临时转置，使得每个转置寄存器包含来自多个连续寄存器的一个字节或字。 通过将存储在寄存器中的任何字节中的值与存储在同一寄存器中的任何其他字节中的值进行交换，程序可以任意重组寄存器中的字节。 还提供间接寄存器访问，无需额外的记分卡硬件，作为从一个寄存器到另一个寄存器的明显移动。 还提供了I / O处的硬件数据FIFO的功能，无需寄存器到寄存器传输的功耗。 但是，可以在程序控制下更改FIFO的大小。

    Flexible Microprocessor Register File
    5.
    发明申请
    Flexible Microprocessor Register File 审中-公开
    灵活的微处理器寄存器文件

    公开(公告)号：US20080082798A1

    公开(公告)日：2008-04-03

    申请号：US11537425

    申请日：2006-09-29

    申请人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    发明人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    IPC分类号： G06F9/44

    CPC分类号： G06F9/30098 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/30141

    摘要： Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

    摘要翻译： 在寄存器文件中以多种格式查看数据的体系结构和方法。 各种公开的实施例允许一个寄存器文件内的多个连续寄存器看起来被一个指令临时转置，使得每个转置寄存器包含来自多个连续寄存器的一个字节或字。 通过将存储在寄存器中的任何字节中的值与存储在同一寄存器中的任何其他字节中的值进行交换，程序可以任意重组寄存器中的字节。 还提供间接寄存器访问，无需额外的记分卡硬件，作为从一个寄存器到另一个寄存器的明显移动。 还提供了I / O处的硬件数据FIFO的功能，无需寄存器到寄存器传输的功耗。 但是，可以在程序控制下更改FIFO的大小。

    Processing Architectures with Typed Instruction Sets
    6.
    发明申请
    Processing Architectures with Typed Instruction Sets 有权
    具有类型化指令集的处理架构

    公开(公告)号：US20080082799A1

    公开(公告)日：2008-04-03

    申请号：US11536483

    申请日：2006-09-28

    申请人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    发明人： Jonathan Bloomfield ,  John Robson ,  Nick Murphy

    IPC分类号： G06F9/44

    CPC分类号： G06F9/30145 ,  G06F9/3013 ,  G06F9/30178 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3822

    摘要： An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).

    摘要翻译： 用于微处理器等的架构，其中指令包括选择几个解释寄存器之一的类型标识符。 解释寄存器保存用于解释每个指令的操作码的信息，使得压缩指令流（具有类型标识符）可以被转换成扩展指令流。 优选地，类型标识符还将定序器指令与处理单元指令区分开，并且甚至可以区分不同类型的定序器指令（以及不同类型的处理单元指令）。