-
1.发明授权Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations 失效使用组合二极管/电阻器结构测量电流和电阻，以监控集成电路制造工艺的变化公开(公告)号：US08709833B2
公开(公告)日：2014-04-29
申请号：US13334632
申请日：2011-12-22
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译： 使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。 每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。 在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。 在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。 然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。
-
2.发明申请MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS 失效使用组合二极管/电阻结构测量电流和电阻监视集成电路制造过程变化公开(公告)号：US20130161615A1
公开(公告)日：2013-06-27
申请号：US13334632
申请日：2011-12-22
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译： 使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。 每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。 在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。 在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。 然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。
-
3.发明申请CORRELATION AND OVERLAY OF LARGE DESIGN PHYSICAL PARTITIONS AND EMBEDDED MACROS TO DETECT IN-LINE DEFECTS 审中-公开大型设计物理分区和嵌入式宏块的相关和覆盖以检测在线缺陷公开(公告)号：US20100174957A1
公开(公告)日：2010-07-08
申请号：US12350261
申请日：2009-01-08
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318511 , G11C2029/0403
摘要： A method of identifying defects in a chip integral to a wafer by correlating physical defects to a corresponding logic fail. The method includes partitioning a logic representation of the chip; identifying physical defects and determining corresponding coordinates of each identified physical defect; determining boundaries of the failing logic partitions, each logic partition being bound by coordinates; and correlating the physical coordinates of the defects to the bounded failing logic partitions. The scaled back, low overhead method correlates design sensitivities and test fails to physical process defects detected during semiconductor manufacturing in-line test inspection. It further identifies and records design physical coordinates of large embedded logic physical partitions test structures, memory arrays, and the like.
摘要翻译： 通过将物理缺陷相关联到相应的逻辑故障来识别与晶片积分的芯片中的缺陷的方法。 该方法包括分割芯片的逻辑表示; 识别物理缺陷并确定每个识别的物理缺陷的对应坐标; 确定故障逻辑分区的边界，每个逻辑分区由坐标约束; 并将缺陷的物理坐标与有界故障逻辑分区相关联。 缩小的低开销方法将设计灵敏度相关联，并且测试不能在半导体制造在线测试检查期间检测到的物理过程缺陷。 它进一步识别和记录大型嵌入式逻辑物理分区测试结构，存储器阵列等的设计物理坐标。
-
4.发明申请METHOD AND SYSTEM FOR CREATING ARRAY DEFECT PARETOS USING ELECTRICAL OVERLAY OF BITFAIL MAPS, PHOTO LIMITED YIELD, YIELD, AND AUTO PATTERN RECOGNITION CODE DATA 审中-公开使用BITFAIL MAPS的电气覆盖创建阵列缺陷二极管的方法和系统，照片有限公司，YIELD和自动图案识别代码数据公开(公告)号：US20080319568A1
公开(公告)日：2008-12-25
申请号：US11766844
申请日：2007-06-22
IPC分类号： G06F19/00
CPC分类号： H01L22/12 , G06T5/50 , G06T7/0004 , G06T2207/30148 , H01L22/22
摘要： A method for creating defect array paretos for semiconductor manufacturing, the method includes: merging a set of ETPLY data {the electrical overlay of bitfail map (BFM) data with inline photo inspection (PLY) data), and auto pattern recognition code (APRC) failure data to create an electrical failure data set along with a set of inline photo inspection defects that caused electrical failures; merging the APRC failure data with wafer final test (WFT) sort data to delineate array failures that are repairable from array failures that are not repairable for the calculation of kill ratios; wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes that are array failures that are not repairable; and wherein the merging of the APRC failure data with the WFT sort data is used to create paretos of APRC codes for semiconductor devices that are repairable at wafer final test.
摘要翻译： 一种用于制造用于半导体制造的缺陷阵列paretos的方法，所述方法包括：将一组ETPLY数据{比特率图（BFM）数据的电覆盖与内联照片检查（PLY）数据））和自动模式识别码（APRC） 故障数据创建电气故障数据集以及导致电气故障的一组内联照片检查缺陷; 将APRC故障数据与晶圆最终测试（WFT）排序数据合并，以描绘可从数组故障中修复的阵列故障，这些阵列故障不能用于计算死亡比率; 其中将APRC故障数据与WFT分类数据的合并用于创建不可修复的阵列故障的APRC代码的伪指令; 并且其中APRC故障数据与WFT分类数据的合并被用于为晶片最终测试可修复的半导体器件创建APRC代码的伪元件。
-
-
-
搜索结果
4 条记录 (耗时 0.013 秒)
