公开(公告)号：US07568180B2

公开(公告)日：2009-07-28

申请号：US10595703

申请日：2005-02-22

Applicant: Hans Eisenmann ,  Kai Peter ,  Dennis Ciplickas ,  Jonathan O. Burrows ,  Yunqiang Zhang Zhang

Inventor： Hans Eisenmann ,  Kai Peter ,  Dennis Ciplickas ,  Jonathan O. Burrows ,  Yunqiang Zhang Zhang

IPC: G06F17/50

CPC classification number: G03F7/705

Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.

Abstract translation: 一种方法包括以下步骤：（a）通过光刻处理在处理器上模拟多个布局图案的制造; （b）基于所述模拟确定所述布局图案对多个参数的敏感度; （c）使用灵敏度来计算每个参数中的每一个的范围内的图案的偏差; 和（d）选择具有最大或接近最大偏差的图案以用作测试图案。

公开(公告)号：US07434197B1

公开(公告)日：2008-10-07

申请号：US11262148

申请日：2005-10-28

Applicant: Christoph Dolainsky ,  Jonathan O. Burrows ,  Dennis Ciplickas ,  Joseph C. Davis ,  Rakesh Vallishayee ,  Howard Read ,  Larg. H. Weiland ,  Christopher Hess

Inventor： Christoph Dolainsky ,  Jonathan O. Burrows ,  Dennis Ciplickas ,  Joseph C. Davis ,  Rakesh Vallishayee ,  Howard Read ,  Larg. H. Weiland ,  Christopher Hess

IPC: G06F17/50

CPC classification number: G03F7/705

Abstract: A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.

Abstract translation: 在面罩布局设计中识别出热点。 热点表示具有容易产生一个或多个制造缺陷的一个或多个特征几何形状的面罩布局设计的局部区域。 为识别的热点产生测试结构。 测试结构被定义为模拟易于产生一个或多个制造缺陷的一个或多个特征几何形状。 使用特定的制造工艺在测试晶片上制造测试结构。 检查制造的测试结构以识别对于掩模布局设计或指定制造工艺的热点的特征几何形状的一个或多个调整，其中所识别的调整能够减少制造缺陷。

公开(公告)号：US20080295061A1

公开(公告)日：2008-11-27

申请号：US10595703

申请日：2005-02-22

Applicant: Hans Eisenmann ,  Kai Peter ,  Dennis Ciplickas ,  Jonathan O. Burrows ,  Yunqiang Zhang Zhang

Inventor： Hans Eisenmann ,  Kai Peter ,  Dennis Ciplickas ,  Jonathan O. Burrows ,  Yunqiang Zhang Zhang

IPC: G06F17/50

CPC classification number: G03F7/705

Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.

Abstract translation: 一种方法包括以下步骤：（a）通过光刻处理在处理器上模拟多个布局图案的制造; （b）基于所述模拟确定所述布局图案对多个参数的敏感度; （c）使用灵敏度来计算每个参数中的每一个的范围内的图案的偏差; 和（d）选择具有最大或接近最大偏差的图案以用作测试图案。