公开(公告)号：US07487474B2

公开(公告)日：2009-02-03

申请号：US10541076

申请日：2003-11-17

申请人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

发明人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

摘要翻译： 集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。 基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。 确定变体设计元素的产出与面积比。 如果变形设计元素的产率与面积之比大于所获得的设计元素的面积比，则变形设计元素被保留以用于设计集成电路。

公开(公告)号：US07434197B1

公开(公告)日：2008-10-07

申请号：US11262148

申请日：2005-10-28

申请人： Christoph Dolainsky ,  Jonathan O. Burrows ,  Dennis Ciplickas ,  Joseph C. Davis ,  Rakesh Vallishayee ,  Howard Read ,  Larg. H. Weiland ,  Christopher Hess

发明人： Christoph Dolainsky ,  Jonathan O. Burrows ,  Dennis Ciplickas ,  Joseph C. Davis ,  Rakesh Vallishayee ,  Howard Read ,  Larg. H. Weiland ,  Christopher Hess

IPC分类号： G06F17/50

CPC分类号： G03F7/705

摘要： A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.

摘要翻译： 在面罩布局设计中识别出热点。 热点表示具有容易产生一个或多个制造缺陷的一个或多个特征几何形状的面罩布局设计的局部区域。 为识别的热点产生测试结构。 测试结构被定义为模拟易于产生一个或多个制造缺陷的一个或多个特征几何形状。 使用特定的制造工艺在测试晶片上制造测试结构。 检查制造的测试结构以识别对于掩模布局设计或指定制造工艺的热点的特征几何形状的一个或多个调整，其中所识别的调整能够减少制造缺陷。

公开(公告)号：US20060101355A1

公开(公告)日：2006-05-11

申请号：US10541076

申请日：2003-11-17

申请人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

发明人： Dennis Ciplickas ,  Joe Davis ,  Christopher Hess ,  Sherry Lee ,  Enrico Malavasi ,  Abdulmobeen Mohammad ,  Ratibor Radojcic ,  Brian Stine ,  Rakesh Vallishayee ,  Stefano Zanella ,  Nicola Dragone ,  Carlo Guardiani ,  Michel Quarantelli ,  Stefano Tonello ,  Joshi Aniruddha

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit

摘要翻译： 集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。 基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。 确定变体设计元素的产出与面积比。 如果变形设计元件的屈服面积比大于获得的设计元素的屈服面积比，则变形设计元素被保留用于设计集成电路