公开(公告)号：US06415361B1

公开(公告)日：2002-07-02

申请号：US09487348

申请日：2000-01-19

申请人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

发明人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F2212/2542

摘要： An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

摘要翻译： 一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。

公开(公告)号：US06505289B1

公开(公告)日：2003-01-07

申请号：US09475049

申请日：1999-12-30

申请人： Jong Seok Han ,  Sang Man Moh ,  Woo Jong Hahn ,  Suk Han Yoon

发明人： Jong Seok Han ,  Sang Man Moh ,  Woo Jong Hahn ,  Suk Han Yoon

IPC分类号： G06F1300

CPC分类号： G06F15/17337

摘要： The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

摘要翻译： 节点连接装置技术领域本发明涉及节点连接装置。 3链节点互连设备和使用该链路节点的并行处理设备可以自由地确定扩展节点，只使用固定的三个连接链路，由于容易划分成2n（n> 1）个节点，因此适合正常的封装方法。 这些装置包括以下节点。 第一个节点分别连接到其他节点的三个链路。 第二节点有三个链路，一个链路连接到第一个节点，另外两个链路负责连接X +方向，X方向。 第三节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Y +方向，Y方向的连接。 第四个节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Z +方向，Z方向的连接。

公开(公告)号：US06314487B1

公开(公告)日：2001-11-06

申请号：US09209429

申请日：1998-12-11

申请人： Jong Seok Hahn ,  Won Sae Sim ,  Woo Jong Hahn ,  Suk Han Yoon

发明人： Jong Seok Hahn ,  Won Sae Sim ,  Woo Jong Hahn ,  Suk Han Yoon

IPC分类号： G06F1300

CPC分类号： G06F13/364

摘要： The present invention relates to a routing control apparatus for performing a round robin arbitration and an adaptive routing control. The present invention relates to a routing controller for performing an arbitration and a routing control which are nucleus functions of the crossbar routing switch and, in particular, to a normal routing controller unit for performing a priority based round robin arbitration and an adaptive routing controller unit for performing an adaptive routing control by adding an adaptive routing switch logic to the normal routing controller.

摘要翻译： 本发明涉及一种用于执行循环仲裁和自适应路由控制的路由控制装置。 本发明涉及一种用于执行仲裁和路由控制的路由选择控制，该路由控制是交叉开关路由交换机的核心功能，特别是涉及用于执行基于优先级的循环仲裁的正常路由控制器单元和自适应路由控制器单元 用于通过将自适应路由交换逻辑添加到正常路由控制器来执行自适应路由控制。

公开(公告)号：US6108766A

公开(公告)日：2000-08-22

申请号：US131891

申请日：1998-08-10

申请人： Woo Jong Hahn ,  Kyong Park ,  Suk Han Yoon

发明人： Woo Jong Hahn ,  Kyong Park ,  Suk Han Yoon

IPC分类号： G06F15/16 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/78

CPC分类号： G06F9/3826 ,  G06F12/0888 ,  G06F15/7864 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3863 ,  G06F9/3877

摘要： The present invention relates to a structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors, wherein a method is used for preserving a state of a register file by using a shadow register file when main processor inputs an instruction of the sub processor in case that an exceptional situation happens under processing of an instruction of sub processor and for rolling back thereafter the preserved state in case there is an information of occurrence of the exceptional situation from the sub processor. Also, in order to solve a problem that cache efficiency is reduced due to the use of a first cache which is relatively small and frequently used, there is suggested a first cache bypassing function. Further, in order to solve a problem that its processing speed is reduced when the main processor transfers instructions in sub processor, it is possible to improve the processors' parallelism and its efficiency by providing an extra register file.

摘要翻译： 本发明涉及具有多个主处理器和子处理器的处理器的结构以及用于共享子处理器的方法，其中使用一种方法来在主处理器上使用影子寄存器文件来保留寄存器文件的状态 在处理子处理器的处理中发生异常情况的情况下输入子处理器的指令，并且在存在来自子处理器的异常情况的发生信息的情况下，将其保存在保存状态之后。 此外，为了解决由于使用相对小且频繁使用的第一高速缓存而导致的高速缓存效率降低的问题，提出了第一高速缓存旁路功能。 此外，为了解决当主处理器在子处理器中传送指令时其处理速度降低的问题，可以通过提供额外的寄存器文件来提高处理器的并行性及其效率。

公开(公告)号：US6061345A

公开(公告)日：2000-05-09

申请号：US941130

申请日：1997-09-30

申请人： Jong Seok Hahn ,  Kyoung Park ,  Woo Jong Hahn ,  Kee Wook Rim

发明人： Jong Seok Hahn ,  Kyoung Park ,  Woo Jong Hahn ,  Kee Wook Rim

IPC分类号： G06F15/16 ,  H04L12/701 ,  H04L12/775 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/947 ,  H04L12/28 ,  H04L12/56 ,  H04Q19/00

CPC分类号： H04L49/1576 ,  H04L45/00 ,  H04L45/583 ,  H04L49/101 ,  H04L49/256 ,  H04L49/45 ,  H04L49/30

摘要： A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port. The present invention has advantages over the prior art that a data expandability can be provided by simply adding a routing switch without re-designing or re-manufacturing the routing switch several times, and that it can be suitably adapted to an interconnection network of a parallel processing system which requires a high expandability and high performance.

摘要翻译： 公开了一种用于构建并行处理计算机的互连网络的路由交换机。 本发明的目的是提供一种具有数据长度的可扩展性和分级结构的可扩展性的分级互连网络的交叉开关。 根据本发明的用于分层互连网络的交叉开关路由开关包括用于控制一个输入端口以执行输入数据的操纵的预定数量的输入控制单元; 横杆核心单元，用于分析由输入控制单元进行的数据传输请求并输出相应的数据; 以及预定数量的输出控制单元，用于控制一个输出端口并接收来自交叉开关核心单元的输出数据以将其输出到输出端口。 本发明具有优于现有技术的优点，通过简单地添加路由交换机而不需要重新设计或重新制造路由交换机多次即可提供数据扩展性，并且可以适当地适应于并行的互连网络 处理系统需要高扩展性和高性能。