公开(公告)号：US4872111A

公开(公告)日：1989-10-03

申请号：US233953

申请日：1988-08-18

申请人： Kevin L. Daberkow ,  Christopher D. Finan ,  Joseph A. Petolino ,  Daniel Carl Sobottka ,  Jeffrey A. Thomas

发明人： Kevin L. Daberkow ,  Christopher D. Finan ,  Joseph A. Petolino ,  Daniel Carl Sobottka ,  Jeffrey A. Thomas

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0855 ,  G06F9/3824

摘要： In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.

摘要翻译： 在包括流水线指令执行单元和流水线高速缓存的数据处理系统中，由一组FIFO寄存器和相关联的支持逻辑组成的存储队列将数据从流水线指令执行单元传送到高速缓存。 当来自指令执行流水线的存储请求流被转发到高速缓存时，代替将数据直接放入高速缓存中，将存储的起始地址，存储长度和要存储的数据放入存储队列之一 注册 指令执行单元将存储请求视为已完成，并且即使数据尚未物理放置在高速缓存中也继续处理。 在高速缓存中的未使用的存储管线周期期间的后续时间内，对高速缓存的写入完成。

公开(公告)号：US4768197A

公开(公告)日：1988-08-30

申请号：US907665

申请日：1986-09-15

申请人： Joseph A. Petolino ,  Christopher D. Finan ,  Jeffrey T. Isozaki ,  Nicholas Y. Pang

发明人： Joseph A. Petolino ,  Christopher D. Finan ,  Jeffrey T. Isozaki ,  Nicholas Y. Pang

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1064

摘要： A system for updating an ECC code over a line in a data store when only part of the line has been updated is described. The system receives the update and its address, decodes the address to generate a first signal identifying the part of the line to be updated and a second signal identifying an un-updated part of the section. The data of the update and the first signal are used to generate a first partial error code. Data from the un-updated part of the line is read as the update is written to the store. The data from the un-updated part of the section and the second signal are used to generate a second partial error code. Finally, the first and second partial error codes are combined to generate the updated error code.

摘要翻译： 描述当仅更新线路的一部分时，在数据存储器中的行上更新ECC代码的系统。 系统接收更新及其地址，对地址进行解码，以产生识别要更新的行的一部分的第一信号和识别该部分的未更新部分的第二信号。 更新和第一信号的数据用于产生第一部分错误代码。 随着更新被写入商店，读取行的未更新部分的数据。 来自部分的未更新部分的数据和第二信号用于生成第二部分错误代码。 最后，组合第一和第二部分错误代码以生成更新的错误代码。

公开(公告)号：US4852100A

公开(公告)日：1989-07-25

申请号：US61847

申请日：1987-06-11

申请人： Harold F. Christensen ,  Jeffrey A. Thomas ,  Jeffrey Isozaki ,  Joseph A. Petolino

发明人： Harold F. Christensen ,  Jeffrey A. Thomas ,  Jeffrey Isozaki ,  Joseph A. Petolino

IPC分类号： G06F11/07 ,  G06F11/10 ,  G06F12/00

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/10 ,  G06F12/00

摘要： The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data in order to minimize delays in the move-in data path, and bypass data paths are provided such that a flow may bypass all error checking and correcting circuitry and cacheing apparatus between the main storage array and the CPU.

摘要翻译： 本发明提供一种用于报告存储在数据处理器的存储装置中的数据中的错误的装置，包括：用于存储多个数字第一信号的第一装置; 用于存储所述多个数字第一信号并适于存储至少一个数字第二信号的第二装置; 用于将所述多个数字第一信号基本上从所述第一装置发送到所述第二装置的第三装置; 第四装置，用于在所述第三装置发送所述第一信号的过程中，响应于在所述多个数字第一信号中的一个或多个中出现一个或多个错误，提供所述至少一个数字第二信号; 用于将所述多个数字第一信号基本上从所述第二装置发送到所述第一装置的第五装置; 以及第六装置，适于在所述第五装置发送所述多个数字第一信号的过程中接收所述至少一个数字第二信号，并响应于所述至少一个数字第二信号的发生而提供至少一个第三信号 。 在每个数据流中，通过多个不同的检查块生成并应用ECC代码，以便最小化移入数据路径中的延迟，并且提供旁路数据路径，使得流可绕过所有错误检查和校正电路，并且 主存储阵列与CPU之间的缓存设备。

公开(公告)号：US4851993A

公开(公告)日：1989-07-25

申请号：US41046

申请日：1987-04-20

申请人： Jack Chen ,  Jeffrey A. Thomas ,  Joseph A. Petolino, Jr. ,  Michael J. Begley ,  Ajay Shah ,  Michael D. Taylor ,  Richard J. Tobias

发明人： Jack Chen ,  Jeffrey A. Thomas ,  Joseph A. Petolino, Jr. ,  Michael J. Begley ,  Ajay Shah ,  Michael D. Taylor ,  Richard J. Tobias

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0888 ,  G06F9/3826

摘要： Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

摘要翻译： 将数据从主存储单元旁路到中间存储单元周围的指令和操作数处理单元，提高了数据处理系统的性能。 指令和操作数处理单元向中间存储单元或高速缓存提供对操作数的请求。 如果从缓存中缺少该行，则从主存储单元检索请求操作数。 旁路数据路径连接在主存储单元之前，在高速缓存中的错误检测装置之前，以及用于将请求的操作数直接传送到指令和操作数处理单元的指令和操作数处理单元。 控制，耦合以接收对操作数的请求以及指令和操作数处理单元的信号，指示和操作数处理单元在数据包括请求的操作数时从旁路数据路径接收所请求的操作数。

公开(公告)号：US4651321A

公开(公告)日：1987-03-17

申请号：US527677

申请日：1983-08-30

申请人： Gary A. Woffinden ,  Joseph A. Petolino, Jr.

发明人： Gary A. Woffinden ,  Joseph A. Petolino, Jr.

IPC分类号： G06F11/10

CPC分类号： G06F11/1012

摘要： Present invention presents a novel mechanism for reducing the amount of storage space necessary to perform error checking and correcting in a storage unit of a data processing machine by utilizing the information present in the parity checking portion of the storage unit.The novel mechanism is based on generating an error checking and correcting code which includes a first portion identifiable by parity bits normally stored with data words in a data storage device and a second portion. The second portion contains fewer bits than required in the prior art for an equivalent level of error checking and correcting and only the second portion is stored. When data is moved out of the storage device, the first portion is identified from the parity bits.

摘要翻译： 本发明提出了一种用于通过利用存在于存储单元的奇偶校验部分中的信息来减少在数据处理机的存储单元中执行错误校验和校正所需的存储空间量的新型机制。 该新颖机制基于产生错误检查和纠正码，该码包括通过数据存储装置和第二部分中的数据字正常存储的奇偶校验位可识别的第一部分。 第二部分包含比现有技术中针对等同的错误检查和校正级别少的比特，并且仅存储第二部分。 当数据从存储设备移出时，从奇偶校验位识别第一部分。

公开(公告)号：US4888689A

公开(公告)日：1989-12-19

申请号：US920805

申请日：1986-10-17

申请人： Michael D. Taylor ,  Robert M. Maier ,  Michael J. Begley ,  Allan J. Zmyslowski ,  Jeffrey A. Thomas ,  Joseph A. Petolino

发明人： Michael D. Taylor ,  Robert M. Maier ,  Michael J. Begley ,  Allan J. Zmyslowski ,  Jeffrey A. Thomas ,  Joseph A. Petolino

IPC分类号： G06F9/38

CPC分类号： G06F9/383

摘要： An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.

摘要翻译： 如果联锁指令可能需要存储单元管理工作，则用于在指令流水线的互锁期间用于提高高速缓存存储单元利用率的装置和方法在互锁的一个周期期间生成控制信号。 响应于控制信号，存储单元中的选择器控制逻辑产生指示由存储单元进行选择的互锁指令的优先信号进行处理。 响应于控制信号和优先级信号，在互锁指令的互锁期间使用高速缓存管理逻辑来准备在互锁被释放时提供所需数据。

公开(公告)号：US4855904A

公开(公告)日：1989-08-08

申请号：US225875

申请日：1988-09-22

申请人： Kevin L. Daberkow ,  Christopher D. Finan ,  Joseph A. Petolino ,  Daniel C. Sobottka ,  Jeffrey A. Thomas

发明人： Kevin L. Daberkow ,  Christopher D. Finan ,  Joseph A. Petolino ,  Daniel C. Sobottka ,  Jeffrey A. Thomas

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3824 ,  G06F12/0855

摘要： In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.

摘要翻译： 在具有用于执行根据第一流水线运行的指令的第一单元和用于存储根据第二流水线运行的多个端口的数据的地址单元的流水线数据处理机中，所述第一单元具有用于保存结果的结果寄存器，包括 第一流水线的数据和地址信息，本发明提供一种用于将结果寄存器中的结果传送到第二单元的装置。 提供连接到结果寄存器的多个寄存器，每个寄存器存储来自第一流水线的至少一个流的结果和存储控制信息。 此外，包括响应于控制信息和第二流水线的与第二单元和多个端口通信的控制器，用于在先入先出的队列中选择多个端口中的一个作为端口 到第二单元并用于更新控制信息。

公开(公告)号：US08108650B2

公开(公告)日：2012-01-31

申请号：US12474783

申请日：2009-05-29

申请人： Joseph A. Petolino, Jr.

发明人： Joseph A. Petolino, Jr.

IPC分类号： G06F9/34

CPC分类号： G06F12/1027 ,  G06F12/0864

摘要： In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.

公开(公告)号：US5095424A

公开(公告)日：1992-03-10

申请号：US384867

申请日：1989-07-21

申请人： Gary A. Woffinden ,  Theodore S. Robinson ,  Jeffrey A. Thomas ,  Robert A. Ertl ,  James P. Millar ,  Christopher D. Finan ,  Joseph A. Petolino ,  Ajay Shah ,  Shen H. Wang ,  Mark Semmelmeyer

发明人： Gary A. Woffinden ,  Theodore S. Robinson ,  Jeffrey A. Thomas ,  Robert A. Ertl ,  James P. Millar ,  Christopher D. Finan ,  Joseph A. Petolino ,  Ajay Shah ,  Shen H. Wang ,  Mark Semmelmeyer

IPC分类号： G06F12/08

CPC分类号： G06F12/0848

摘要： A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

摘要翻译： 描述了实现多个中央处理单元的计算机系统架构，每个中央处理单元包括分割指令和操作数高速缓存，并且通过使用线对状态来管理存储器线的多个副本（线对）。 当对指令和操作数数据高速缓存存储器进行传输时，对存储器线路的系统管理允许始终保持系统的完整性。 分割高速缓存架构管理确定在指令和操作数高速缓存存储器内是否存在具有第一预定系统地址的存储器线，或者将在存储器线路中移入。 维持地址标签线对状态信息以允许确定各个存储器线对成员是否存在和在何处驻留。 该架构在将存储器线路的每次传送到系统的任何分割高速缓存时实现线对的管理。 只要在单个中央处理器的每个指令和操作数缓存缓冲器中的相同相对位置存在相同的存储器线，就允许线对存在。 该架构还包括数据路径选择器，用于根据操作数缓冲目标是作为线对的成员的存储线，将操作数数据传送到指令或操作数数据高速缓冲存储器或两者。

公开(公告)号：US4625273A

公开(公告)日：1986-11-25

申请号：US527672

申请日：1983-08-30

申请人： Gary A. Woffinden ,  Joseph A. Petolino, Jr.

发明人： Gary A. Woffinden ,  Joseph A. Petolino, Jr.

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC分类号： G06F11/0751 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/104

摘要： An apparatus for enhancing the speed of access of an execution unit in a data processing machine to the high speed buffer memory array by storing data from the execution unit in the buffer before completing error checking operations.

摘要翻译： 一种用于通过在完成错误检查操作之前将来自执行单元的数据存储在缓冲器中来将数据处理机器中的执行单元访问速度提高到高速缓冲存储器阵列的装置。