公开(公告)号：US11213234B1

公开(公告)日：2022-01-04

申请号：US17336587

申请日：2021-06-02

申请人： Zavdi Lichtman ,  Joseph Drori

发明人： Zavdi Lichtman ,  Joseph Drori

IPC分类号： G06T7/62 ,  A61B5/20 ,  H04N7/18 ,  G01F1/66 ,  G06T7/246 ,  H04N5/33 ,  G06T7/00

摘要： It is a principal goal of the present invention is to provide a uroflowmetry device for calculating uroflowmetry data (flow rate and other data) associated with urination sessions. The invention is an in-toilet uroflowmetry device, which unlike existing stand-alone and in-toilet devices is not touched by the urine stream, and un-like with existing in-toilet devices, the toilet is useable for all normal functions by men and women.
The invention also provides new data not provided by existing uroflowmetry devices.
The present invention is a device comprised of an electronic open loop belt with video cameras, a single-board computer (SBC), LEDs and various sensors to start the video cameras and control the LEDs. The video data is transferred wirelessly to a website where image processing is performed on the video data, followed by computations of flow rate and additional uroflowmetry data.

公开(公告)号：US07039150B1

公开(公告)日：2006-05-02

申请号：US09620308

申请日：2000-07-20

申请人： Joseph Drori

发明人： Joseph Drori

IPC分类号： H04L23/00

CPC分类号： H02J7/0022 ,  H02J7/0004

摘要： A serial communication method and system is provided for use with a battery management system. The system includes a port capable of sending and receiving pulses over a single conductor, serial interface logic compatible with a serial protocol and capable of generating and detecting signals on the port and communicating the signals with an internal bus in the battery management system wherein each signal in the serial protocol is defined by a specific number of pulses. In the serial protocol, a zero signal corresponds to a sequence of two pulses, a one signal corresponds to a sequence of three pulses, an acknowledge signal corresponds to a sequence of four pulses, and a start signal corresponds to a sequence of five pulses.

摘要翻译： 提供串行通信方法和系统用于电池管理系统。 该系统包括能够通过单个导体发送和接收脉冲的端口，与串行协议兼容的串行接口逻辑，并且能够生成和检测端口上的信号并与电池管理系统中的内部总线通信信号，其中每个信号 在串行协议中由特定数量的脉冲定义。 在串行协议中，零信号对应于两个脉冲的序列，一个信号对应于三个脉冲的序列，确认信号对应于四个脉冲的序列，并且起始信号对应于五个脉冲的序列。

公开(公告)号：US20210401341A1

公开(公告)日：2021-12-30

申请号：US17336587

申请日：2021-06-02

申请人： Zavdi Lichtman ,  Joseph Drori

发明人： Zavdi Lichtman ,  Joseph Drori

IPC分类号： A61B5/20 ,  H04N7/18 ,  H04N5/33 ,  G06T7/00 ,  G06T7/246 ,  G06T7/62 ,  G01F1/66

摘要： It is a principal goal of the present invention is to provide a uroflowmetry device for calculating uroflowmetry data (flow rate and other data) associated with urination sessions. The invention is an in-toilet uroflowmetry device, which unlike existing stand-alone and in-toilet devices is not touched by the urine stream, and un-like with existing in-toilet devices, the toilet is useable for all normal functions by men and women.
The invention also provides new data not provided by existing uroflowmetry devices.
The present invention is a device comprised of an electronic open loop belt with video cameras, a single-board computer (SBC), LEDs and various sensors to start the video cameras and control the LEDs. The video data is transferred wirelessly to a website where image processing is performed on the video data, followed by computations of flow rate and additional uroflowmetry data.

公开(公告)号：US06555996B2

公开(公告)日：2003-04-29

申请号：US10007602

申请日：2001-11-13

申请人： Joseph Drori ,  Allan Ming-Lun Lin

发明人： Joseph Drori ,  Allan Ming-Lun Lin

IPC分类号： H03H100

CPC分类号： H03H7/24

摘要： Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer comprises a first main terminal, a second main terminal, a wiper terminal, and a resistor stack comprising a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of RS ohms. The potentiometer further comprises a first variable resistance network coupled between one end of the resistor stack and the potentiometer's first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer's second main terminal. The first variable resistance network has a variable resistance value R1 which varies between zero ohms and RP ohms. The second variable resistance network has a variable resistance value R2 which is maintained substantially at value of (RP−R1). The wiper terminal is selectively coupled to one of the internal nodes of the resistor stack, or to one of the ends of the resistor stack, to provide a coarse setting of the potentiometer's wiper position. The resistances of the variable resistance networks are changed to provide the fine resolution for the potentiometer's wiper position. The present invention provides a large number of discrete wiper positions with a constant end-to-end resistance, while using a small number of resistors and transistors relative to prior art implementations. A further advantage of the invention is that the potentiometer may be constructed with a small number of selection transistors turned on within the current path between the potentiometer's main terminals, thereby providing higher accuracy.

公开(公告)号：US5161157A

公开(公告)日：1992-11-03

申请号：US802005

申请日：1991-11-27

申请人： William H. Owen ,  John Caywood ,  Joseph Drori ,  James Jaffe ,  Isao Nojima ,  Jeffrey Sung ,  Ping Wang

发明人： William H. Owen ,  John Caywood ,  Joseph Drori ,  James Jaffe ,  Isao Nojima ,  Jeffrey Sung ,  Ping Wang

IPC分类号： G06F11/00 ,  G11C29/00

CPC分类号： G11C29/789 ,  G06F11/006 ,  G11C29/835 ,  G11C29/838

摘要： A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

摘要翻译： 公开了一种用于集成电路半导体存储器阵列的现场可编程冗余装置。 本发明允许用户在集成电路存储器阵列处于现场时用冗余存储器单元替换有缺陷的存储单元。 用户通过集成电路半导体存储器阵列的标准信号路径与标准电压电平与冗余设备进行通信。 冗余设备在存储器阵列的一个或多个地址和数据线上检测预定的代码序列，以进入特殊的冗余重新配置模式。 在重新配置模式中，冗余设备提供关于冗余存储器单元的可用性和功能的信息，并且使得用户能够用所选择的冗余存储器单元来替换有缺陷的存储器单元。 现场可编程冗余设备可以包括非易失性存储器装置，例如EEPROM，用于存储具有冗余存储器单元的主存储器单元的替换。 在重新配置模式中，第二预定代码序列的检测导致重新配置模式被退出。

公开(公告)号：US06331768B1

公开(公告)日：2001-12-18

申请号：US09593734

申请日：2000-06-13

申请人： Joseph Drori ,  Allan Ming-Lun Lin

发明人： Joseph Drori ,  Allan Ming-Lun Lin

IPC分类号： H03H100

CPC分类号： H03H7/24

摘要： Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer has a first main terminal, a second main terminal, a wiper terminal, and a resistor stack having a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of RS ohms. The potentiometer further has a first variable resistance network coupled between one end of the resistor stack and the potentiometer's first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer's second main terminal. The first variable resistance network has a variable resistance value R1 which varies between zero ohms and RP ohms. The second variable resistance network has a variable resistance value R2 which is maintained substantially at value of (RP−R1). The wiper terminal is selectively coupled to one of the internal nodes of the resistor stack, or to one of the ends of the resistor stack, to provide a coarse setting of the potentiometer's wiper position. The resistances of the variable resistance networks are changed to provide the fine resolution for the potentiometer's wiper position. The present invention provides a large number of discrete wiper positions with a constant end-to-end resistance, while using a small number of resistors and transistors relative to prior art implementations.

摘要翻译： 公开了具有高分辨率和高精度的固态电位计。 示例性电位器具有第一主端子，第二主端子，擦拭器端子和电阻器堆叠，其具有在多个M-1内部节点处彼此串联耦合的多个M个电阻器。 堆叠中的每个电阻器具有基本上相同的RS欧姆值。 电位计还具有耦合在电阻器堆叠的一端和电位器的第一主端子之间的第一可变电阻网络，以及耦合在电阻器堆叠的另一端和电位器的第二主端子之间的第二可变电阻网络。 第一可变电阻网络具有在零欧姆和RP欧姆之间变化的可变电阻值R1。 第二可变电阻网络具有基本上保持（RP-R1）的值的可变电阻值R2。 刮水器端子选择性地耦合到电阻器堆叠的一个内部节点，或者耦合到电阻器堆叠的一个端部，以提供电位器的抽头位置的粗略设置。 改变可变电阻网络的电阻，为电位器的抽头位置提供精细的分辨率。 本发明提供了大量具有恒定端对端电阻的离散抽头位置，同时相对于现有技术实现使用少量电阻器和晶体管。

公开(公告)号：US5153880A

公开(公告)日：1992-10-06

申请号：US491749

申请日：1990-03-12

申请人： William H. Owen ,  John Caywood ,  Joseph Drori ,  James Jaffe ,  Isao Nojima ,  Jeffrey Sung ,  Ping Wang

发明人： William H. Owen ,  John Caywood ,  Joseph Drori ,  James Jaffe ,  Isao Nojima ,  Jeffrey Sung ,  Ping Wang

IPC分类号： G11C29/00

CPC分类号： G11C29/789 ,  G11C29/835 ,  G11C29/838

摘要： A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundance apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

摘要翻译： 公开了一种用于集成电路半导体存储器阵列的现场可编程冗余装置。 本发明允许用户在集成电路存储器阵列处于现场时用冗余存储器单元替换有缺陷的存储单元。 用户通过具有集成电路半导体存储器阵列的标准电压电平的标准信号路径与冗余设备进行通信。 冗余设备在存储器阵列的一个或多个地址和数据线上检测预定的代码序列，以进入特殊的冗余重新配置模式。 在重新配置模式中，冗余设备提供关于冗余存储器单元的可用性和功能的信息，并且使得用户能够用所选择的冗余存储器单元来替换有缺陷的存储器单元。 现场可编程冗余装置可以包括诸如EEPROM的非易失性存储装置，以存储具有冗余存储器单元的主存储器单元的替换。 在重新配置模式中，第二预定代码序列的检测导致重新配置模式被退出。

公开(公告)号：US4668932A

公开(公告)日：1987-05-26

申请号：US759599

申请日：1985-07-26

申请人： Joseph Drori ,  William S. J. Check

发明人： Joseph Drori ,  William S. J. Check

IPC分类号： H03H7/24 ,  G11C17/14 ,  H03H7/25 ,  H01C10/16

CPC分类号： G11C17/14 ,  H03H7/25

摘要： A variable impedance circuit for use in an external circuit. The impedance value may be altered by an external circuit. The invention consists of a plurality of two terminal impedance elements connected in series. A node is provided between each pair of impedance elements in the series chain. At least one of the first element and last elements in the series chain are connected to terminals which are accessible for connection to the external circuit. Each of the nodes may be connected to a terminal which is also accessible for connection to the external circuit. An electrically reprogrammable read-only memory stores the identity of the node connected such that the identity of this node is retained when power is removed from the invention. When power is returned to the invention, the node which was previously connected to the terminal is automatically reconnected.

摘要翻译： 用于外部电路的可变阻抗电路。 阻抗值可能由外部电路改变。 本发明由多个串联连接的两个端子阻抗元件组成。 在串联链中的每对阻抗元件之间提供节点。 串联链中的第一元件和最后元件中的至少一个连接到可连接到外部电路的端子。 每个节点可以连接到也可以连接到外部电路的终端。 电可重新编程的只读存储器存储连接的节点的身份，使得当从本发明中移除电力时该节点的身份被保留。 当电源返回到本发明时，先前连接到终端的节点被自动重新连接。

公开(公告)号：US06501249B1

公开(公告)日：2002-12-31

申请号：US09620089

申请日：2000-07-20

申请人： Joseph Drori

发明人： Joseph Drori

IPC分类号： H02J704

CPC分类号： G01R31/3613 ,  H02J7/0031 ,  H02J7/044 ,  H02J2007/0037 ,  H02J2007/0039 ,  H02J2007/005

摘要： A battery management system is provided having a battery management unit (BMU) and an integrated switch and sense device (SSD) for accurately measuring the charge state of a rechargeable battery and providing charge protection for the rechargeable battery. The system includes a load, a integrated power and sense device including a power device and a sense device, the integrated power and sense device connected between the rechargeable battery and the load wherein the sense device provides a mirror current proportional to the current in the power device, a first circuit that measures the rechargeable battery current using the mirror current, and a second circuit that measures the charge in the rechargeable battery using the mirror current.

摘要翻译： 提供具有电池管理单元（BMU）和集成开关和感测装置（SSD）的电池管理系统，用于精确测量可再充电电池的充电状态并为可再充电电池提供电荷保护。 该系统包括负载，集成电力和感测装置，其包括功率器件和感测器件，连接在可充电电池和负载之间的集成电力和感测装置，其中感测装置提供与电力中的电流成比例的镜电流 装置，使用镜电流测量可再充电电池电流的第一电路，以及使用镜电流测量可再充电电池中的电荷的第二电路。

公开(公告)号：US5084667A

公开(公告)日：1992-01-28

申请号：US462311

申请日：1989-12-22

申请人： Joseph Drori ,  William S. Jennings Check ,  William H. Owen, III

发明人： Joseph Drori ,  William S. Jennings Check ,  William H. Owen, III

IPC分类号： G05B19/07 ,  G11C17/14 ,  H03H7/25

CPC分类号： G11C17/14 ,  G05B19/075 ,  H03H7/25 ,  G05B2219/23029 ,  G05B2219/23041

摘要： A variable impedance circuit for use in an external circuit is disclosed. The impedance value is selected by an external circuit. The variable impedance is generated between two terminals which are accessible for connection to external circuitry. The impedance provided between these terminals is determined by a control circuit responsive to electrical signals coupled to the control circuit. An internal register in the control circuit stores a value which specifies the impedance between the two terminals. The stored value is copied into a programmable nonvolatile read-only memory in response to a first predetermined electrical signal. Similarly, the value stored in the read-only memory is selectively copied into the internal control circuit register in response to a second predetermined electrical signal. A number of embodiments of variable impedance elements are disclosed which minimize the number of separate resistors required to achieve the equivalent resolution achievable using a series arrangement of resistors.

摘要翻译： 公开了一种用于外部电路的可变阻抗电路。 阻抗值由外部电路选择。 在可连接外部电路的两个端子之间产生可变阻抗。 这些端子之间提供的阻抗由响应耦合到控制电路的电信号的控制电路决定。 控制电路中的内部寄存器存储指定两个端子之间的阻抗的值。 响应于第一预定电信号将存储的值复制到可编程非易失性只读存储器中。 类似地，响应于第二预定电信号，将存储在只读存储器中的值选择性地复制到内部控制电路寄存器中。 公开了可变阻抗元件的多个实施例，其最小化实现使用电阻器的串联布置可实现的等效分辨率所需的单独电阻器的数量。