公开(公告)号：US6063132A

公开(公告)日：2000-05-16

申请号：US105731

申请日：1998-06-26

申请人： William Frantz DeCamp ,  Laurice Thorsen Earl ,  Jason Steven Minahan ,  James Robert Montstream ,  Daniel John Nickel ,  Joseph James Oler, Jr. ,  Richard Quimby Williams

发明人： William Frantz DeCamp ,  Laurice Thorsen Earl ,  Jason Steven Minahan ,  James Robert Montstream ,  Daniel John Nickel ,  Joseph James Oler, Jr. ,  Richard Quimby Williams

IPC分类号： G06F17/50 ,  G06F15/18

CPC分类号： G06F17/5081

摘要： A method using a generate-and-verify computer program product to generate by repetitive passes a design rules checking computer program, wherein the design rules are described in a file called a runset. The design rules checking program is used for exhaustive testing of VLSI chips for compliance to the design rules of a given VLSI fabrication process. The runset is repeatedly iterated in loop fashion with respect to a testcase file containing groups of layout structures or shapes used for verifying the correctness of the runset. A general purpose shapes processing program creates an error shapes file for storing geometrical errors found in each said layout structure. Two additional shapes are used in the verification process: user boundary shapes for defining areas in which errors are not to be detected for a given design rule, and automated boundary shapes created to surround each said layout structure with a boundary that defines regions where error shapes can occur. An association table is created which is a compilation of the error shapes, user boundary shapes, and automated boundary shapes associated with each layout structure. The association table is processed to determine the correctness of the runset. The runset is modified to correct each valid error. The repetitive passes continue until a final runset is generated. This final runset becomes the input to design rules checking computer program product and customizes the program for a given VLSI fabrication process.

摘要翻译： 一种使用生成和验证计算机程序产品通过重复传递生成设计规则检查计算机程序的方法，其中设计规则在称为runset的文件中描述。 设计规则检查程序用于VLSI芯片的详尽测试，以符合给定的VLSI制造工艺的设计规则。 相对于包含用于验证运行集合的正确性的布局结构或形状的组的测试用例文件，运行环以循环方式重复迭代。 通用形状处理程序创建用于存储在每个所述布局结构中发现的几何错误的错误形状文件。 在验证过程中使用两种额外的形状：用于定义不能针对给定设计规则检测错误的区域的用户边界形状，以及围绕每个所述布局结构创建的自动边界形状，其边界限定了错误形状 可以发生。 创建关联表，其是与每个布局结构相关联的错误形状，用户边界形状和自动边界形状的汇编。 处理关联表以确定运行集的正确性。 修改运行集以更正每个有效错误。 重复的传递将继续，直到生成最后的运行。 这个最终的运行成为设计规则检查计算机程序产品的输入，并为给定的VLSI制造过程定制程序。

公开(公告)号：US20100174503A1

公开(公告)日：2010-07-08

申请号：US12349698

申请日：2009-01-07

申请人： Bruce Balch ,  Anthony Wayne Fazekas ,  Mark C.H. Lamorey ,  Jeffrey H. Oppold ,  Joseph James Oler, JR. ,  Chirstopher Daniel Parkinson

发明人： Bruce Balch ,  Anthony Wayne Fazekas ,  Mark C.H. Lamorey ,  Jeffrey H. Oppold ,  Joseph James Oler, JR. ,  Chirstopher Daniel Parkinson

IPC分类号： G01R29/02 ,  G21C17/00 ,  H03K3/03

CPC分类号： G01R31/2621 ,  G01R31/2648 ,  H01L22/34

摘要： An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance.

摘要翻译： 在CMOS器件处理中用于直接测量NFET晶体管相对于PFET晶体管的性能偏移的装置包括一个环形振荡器，其频率用于测量随机跨越芯片变化以及跨芯片变化的相关性; 具有由环形振荡器驱动的输入的平衡逆变器，其中平衡逆变器被设计成形成为使得逆变器的一个或多个NFET器件的电流驱动能力基本上等于一个或多个PFET器件的电流驱动能力 在给定的工作温度下; 以及耦合到反相器的输出的电容器，电容器两端的电压指示在NFET器件性能和PFET器件性能之间是否存在偏斜。