公开(公告)号：US20060190857A1

公开(公告)日：2006-08-24

申请号：US11053078

申请日：2005-02-08

申请人： Robert Likovich ,  Joseph Mendenhall ,  John Morris ,  Robert Reese ,  Chad Winemiller

发明人： Robert Likovich ,  Joseph Mendenhall ,  John Morris ,  Robert Reese ,  Chad Winemiller

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.

摘要翻译： 公开了用于I / O总线的功能仿真的方法，系统和媒体。 更具体地，公开了一种模拟I / O总线的失真和噪声参数的方法。 实施例包括约束记录的一个或多个字段并且基于所得到的参数来确定延迟量，其中最终延迟量包括延迟缓冲器和与参数相关联的延迟量的净值。 实施例还可以包括确定要发送到I / O总线的下一位的值，并且在等待延迟量之后，将总线上的位驱动到下一个位值。 参数可能包括这些参数中的任何一个的偏移，抖动，占空比失真，电压参考失真和漂移。 另外的实施例可以包括响应于满足相位完成条件来发信号通知相位的结束。

公开(公告)号：US20060190871A1

公开(公告)日：2006-08-24

申请号：US11053220

申请日：2005-02-08

申请人： Robert Likovich ,  Joseph Mendenhall ,  John Morris ,  David Otero ,  Chad Winemiller

发明人： Robert Likovich ,  Joseph Mendenhall ,  John Morris ,  David Otero ,  Chad Winemiller

IPC分类号： G06F17/50

CPC分类号： G01R31/318314

摘要： Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.

摘要翻译： 公开了用于管理可参数化设计的功能验证的方法，系统和媒体。 实施例包括具有测试台配置模块的系统，该测试台配置模块适于配置测试台，测试台具有测试台信号，以及具有多个通用设计端口的一个或多个实例组件，其中测试台信号被连接到多个端口。 测试台还可以具有基于芯片特定版本的设计的一个或多个实例化的特殊组件，其中特殊组件被连接到与通用设计相同的端口。 该系统还可以包括功能验证管理器，其通过组件模块观察测试台中的值并且基于所观察到的值自动配置验证环境，包括在不同层次结构中自动插入检查器。 在一些实施例中，测试台可以是VHDL或Verilog测试台。

公开(公告)号：US20070245282A1

公开(公告)日：2007-10-18

申请号：US11279237

申请日：2006-04-10

申请人： Charles Alley ,  Robert Likovich ,  Joseph Mendenhall ,  Chad Winemiller

发明人： Charles Alley ,  Robert Likovich ,  Joseph Mendenhall ,  Chad Winemiller

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Systems, methods, and media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.

摘要翻译： 公开了用于在具有动态范围的结构中使用项目或组件的相对定位的系统，方法和介质，例如用于集成电路（IC）的弹性I / O总线设计。 实施例可以包括具有表示结构内的相对实例位置的用户定义类型的用户定义类型模块。 实施例还可以包括翻译帮助器模块，用于接收与层级相关联的信息并返回与层级相关联的位置信息，以及翻译模块，用于基于一个或多个用户定义的类型在实例的特定位置和相对位置之间进行转换 和从翻译助手模块返回的位置信息以生成翻译结果的列表。 翻译模块的其他实施例可以包括将特定位置转换为相对位置的相对位置确定器，并且还可以包括将相对位置转换为特定位置的特定位置确定器。

公开(公告)号：US20060182187A1

公开(公告)日：2006-08-17

申请号：US11055807

申请日：2005-02-11

申请人： Robert Likovich ,  Robert Reese ,  Joseph Mendenhall ,  Kenneth Barker

发明人： Robert Likovich ,  Robert Reese ,  Joseph Mendenhall ,  Kenneth Barker

IPC分类号： H04B3/00

CPC分类号： H04L1/22 ,  H04L1/242

摘要： A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M−1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.

摘要翻译： 测试模式被加载到驱动器数据移位寄存器中，并通过M位总线（0到M-1）从驱动器芯片发送到接收芯片。 测试模式也在接收芯片处产生，用于与实际接收的数据进行比较。 失败的比较被存储为位错误寄存器（BER）中的逻辑比较。 计数器通过从BER计数逻辑值来确定故障次数。 错误位置计数器的内容被锁存在错误位置锁存器中，用于将逻辑1（在错误位位置）加载到接收器芯片和驱动器芯片中的菊花链自愈控制寄存器（SCR）中。 在错误位隔离故障位路径并添加位位置M中的备用位路径之后，SCR将逻辑1设置为所有位位置。