Method for optimizing automatic place and route layout for full scan
circuits
    1.
    发明授权
    Method for optimizing automatic place and route layout for full scan circuits 失效
    优化全扫描电路自动布局布局的方法

    公开(公告)号:US5208764A

    公开(公告)日:1993-05-04

    申请号:US605557

    申请日:1990-10-29

    摘要: A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

    摘要翻译: 一种包括触发器电路,缓冲器和组合电路元件的计算机集成电路装置,其中触发器电路以可连接到那些触发器电路的驱动信号的缓冲器排成行,触发器电路具有 导体被设计为承载布置成横穿触发器电路的宽度的全局信号,并提供输入和输出端子以匹配相邻触发器电路的输入和输出端子。

    Method for optimizing automatic place and route layout for full scan
circuits
    2.
    发明授权
    Method for optimizing automatic place and route layout for full scan circuits 失效
    优化全扫描电路自动布局布局的方法

    公开(公告)号:US5307286A

    公开(公告)日:1994-04-26

    申请号:US988468

    申请日:1992-12-10

    摘要: A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

    摘要翻译: 一种包括触发器电路,缓冲器和组合电路元件的计算机集成电路装置,其中触发器电路以可连接到那些触发器电路的驱动信号的缓冲器排成行,触发器电路具有 导体被设计为承载布置成横穿触发器电路的宽度的全局信号,并提供输入和输出端子以匹配相邻触发器电路的输入和输出端子。