公开(公告)号：US5307286A

公开(公告)日：1994-04-26

申请号：US988468

申请日：1992-12-10

申请人： Stefan Rusu ,  Joseph S. Yang

发明人： Stefan Rusu ,  Joseph S. Yang

IPC分类号： H01L21/82 ,  G01R31/3185 ,  G06F17/50 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H03K19/173

CPC分类号： H01L27/0207 ,  G01R31/318583 ,  G06F17/5068

摘要： A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

摘要翻译： 一种包括触发器电路，缓冲器和组合电路元件的计算机集成电路装置，其中触发器电路以可连接到那些触发器电路的驱动信号的缓冲器排成行，触发器电路具有 导体被设计为承载布置成横穿触发器电路的宽度的全局信号，并提供输入和输出端子以匹配相邻触发器电路的输入和输出端子。

公开(公告)号：US5208764A

公开(公告)日：1993-05-04

申请号：US605557

申请日：1990-10-29

申请人： Stefan Rusu ,  Joseph S. Yang

发明人： Stefan Rusu ,  Joseph S. Yang

IPC分类号： H01L21/82 ,  G01R31/3185 ,  G06F17/50 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04

CPC分类号： H01L27/0207 ,  G01R31/318583 ,  G06F17/5068

摘要： A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

摘要翻译： 一种包括触发器电路，缓冲器和组合电路元件的计算机集成电路装置，其中触发器电路以可连接到那些触发器电路的驱动信号的缓冲器排成行，触发器电路具有 导体被设计为承载布置成横穿触发器电路的宽度的全局信号，并提供输入和输出端子以匹配相邻触发器电路的输入和输出端子。

公开(公告)号：US20140181596A1

公开(公告)日：2014-06-26

申请号：US13723304

申请日：2012-12-21

申请人： Stefan Rusu ,  Zhiguo Wang ,  Krishnakanth V. Sistla

发明人： Stefan Rusu ,  Zhiguo Wang ,  Krishnakanth V. Sistla

IPC分类号： G06F11/34

CPC分类号： G06F11/3409 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3058

摘要： Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units.

摘要翻译： 公开了用于多个功能硬件单元的磨损均衡技术。 集成电路包括功率控制单元（PCU），其被配置为监视由集成电路的多个功能硬件单元引起的磨损指标。 PCU根据所监视的指示器来计算功能硬件单元的累计磨损量度，并执行均衡动作以均衡功能硬件单元的累积磨损量度。

公开(公告)号：US07657767B2

公开(公告)日：2010-02-02

申请号：US11174204

申请日：2005-06-30

申请人： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

发明人： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/32 ,  G06F1/3287 ,  G11C11/417 ,  Y02D10/171

摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

摘要翻译： 在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。 本文公开了其它实施例。 睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。 高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。 有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。

公开(公告)号：US20050180488A1

公开(公告)日：2005-08-18

申请号：US11035467

申请日：2005-01-13

申请人： Stefan Rusu ,  Simon Tam

发明人： Stefan Rusu ,  Simon Tam

IPC分类号： G01K1/02 ,  G01K7/42 ,  G06F1/20 ,  G01K7/00 ,  G01K13/00 ,  G01K1/08

CPC分类号： G06F1/206 ,  G01K1/026 ,  G01K7/42 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

公开(公告)号：US06908227B2

公开(公告)日：2005-06-21

申请号：US10227125

申请日：2002-08-23

申请人： Stefan Rusu ,  Simon M. Tam

发明人： Stefan Rusu ,  Simon M. Tam

IPC分类号： G01K1/02 ,  G01K7/42 ,  G06F1/20 ,  G01K13/00 ,  G06F1/32

CPC分类号： G06F1/206 ,  G01K1/026 ,  G01K7/42 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

摘要翻译： 描述了一种用于管理具有多核微处理器的集成电路的温度的装置。 具体来说，热传感器放置在每个微处理器核心的潜在热点。 热管理单元监视热传感器。 如果热传感器识别热点，则热管理单元相应地调整该微处理器核心的工作频率和电压。

公开(公告)号：US06788156B2

公开(公告)日：2004-09-07

申请号：US10456660

申请日：2003-06-06

申请人： Simon M. Tam ,  Stefan Rusu

发明人： Simon M. Tam ,  Stefan Rusu

IPC分类号： H03B2800

CPC分类号： G06F1/324 ,  G06F1/3203 ,  H03L7/06 ,  H03L7/0805 ,  Y02D10/126

摘要： A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

摘要翻译： 一种在处理器中动态地改变时钟频率的方法。 一个实施例的方法包括用来自相位锁定环（PLL）的时钟输出来驱动时钟分配网络。 可调时钟发生器与锁相环锁定。 可调时钟发生器代替时钟分配网络上的PLL。

公开(公告)号：US6092212A

公开(公告)日：2000-07-18

申请号：US996305

申请日：1997-12-22

申请人： Harry Muljono ,  Stefan Rusu

发明人： Harry Muljono ,  Stefan Rusu

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4072

摘要： A method and strobe circuit are provided for maintaining a strobe signal at a valid voltage level. The method includes driving the strobe signal at the valid voltage level using a first strobe driver, pre-driving the strobe signal at the valid voltage level using a second strobe driver while the first strobe driver is driving, and terminating the driving of the first strobe driver. The strobe circuit includes a strobe line, a first strobe driver having a first enable input for enabling the first strobe driver and adapted to drive the strobe line with a first strobe signal, and a second strobe driver having a second enable input for enabling the second strobe driver and adapted to drive the strobe line with a second strobe signal. A first strobe controller is coupled to the second enable input and adapted to enable the second strobe driver to pre-drive the second strobe signal while the first strobe driver is enabled, wherein the first and second strobe signals are at equal logic levels.

摘要翻译： 提供了一种用于将选通信号保持在有效电压电平的方法和选通电路。 该方法包括使用第一选通驱动器以有效电压电平驱动选通信号，在第一选通驱动器正在驱动时，使用第二选通驱动器以有效电压电平预驱动选通信号，并终止第一选通脉冲的驱动 司机。 选通电路包括选通线，第一选通驱动器具有第一使能输入，用于启用第一选通驱动器，并且适于用第一选通信号驱动选通线;以及第二选通驱动器，具有第二使能输入， 选通驱动器，并且适于用第二选通信号驱动频闪线。 第一选通控制器耦合到第二使能输入，并且适于使第二选通驱动器在第一选通驱动器被使能的同时预驱动第二选通信号，其中第一和第二选通信号处于相等的逻辑电平。

公开(公告)号：US5581473A

公开(公告)日：1996-12-03

申请号：US605800

申请日：1996-02-23

申请人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

发明人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  Y10S707/99931

摘要： A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository. The timing constraint generator in cooperation with the timing model generator and at least one timing analysis tool generates the timing constraints for the various functional block instances, using the stored information in the repository, the generated timing models of the functional blocks, and a number of timing analysis scripts.

摘要翻译： 提供存储库，加载器，模型生成器，约束生成器和多个时序分析工具，用于管理定时需求规范和测量，以及生成VLSI电路的定时模型和约束。 存储库存储每个针脚实例的时序规格和测量值，每个流程通过圆弧实例。 定时规范和测量由其类别标识，包括至少一个当前规范类别和至少一个测量类别，用于一个时序分析工具。 另外，存储库存储每个引脚实例的多个特性，每个网络的引脚组成以及功能块实例的分层关系。 加载器将各种信息加载到存储库中。 定时模型生成器使用存储库中存储的信息生成各种功能块的时序模型。 与定时模型发生器和至少一个定时分析工具协作的时序约束生成器使用存储库中存储的信息，生成的功能块的定时模型和多个功能块的时间模型来生成各种功能块实例的时序约束 时序分析脚本。

公开(公告)号：US20140184349A1

公开(公告)日：2014-07-03

申请号：US13730629

申请日：2012-12-28

申请人： Harry Muljono ,  Donald L. Faw ,  Charlie Lin ,  Stefan Rusu

发明人： Harry Muljono ,  Donald L. Faw ,  Charlie Lin ,  Stefan Rusu

IPC分类号： H03K7/02

CPC分类号： H03K7/02

摘要： Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.

摘要翻译： 用于配置逻辑以实现信号调制的技术和机制。 在一个实施例中，逻辑包括包括电路的有限脉冲响应（FIR）模块。 选择电路可以用于同时从FIR模块的锁存电路接收信号，并且基于该信号来选择选择电路的输入组并输出电压标识符。 在另一个实施例中，配置逻辑可操作以设置操作模式，其确定由FIR模块接收的并发输入信号的总数，FIR模块将使用该模式来选择用于生成表示电压电平的输出的输入组。