公开(公告)号：US07733169B2

公开(公告)日：2010-06-08

申请号：US12151503

申请日：2008-05-07

申请人： Joy Y. Zhang ,  Viola Schaffer

发明人： Joy Y. Zhang ,  Viola Schaffer

IPC分类号： H03F1/02

CPC分类号： H03F3/005 ,  H03F3/387 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/408 ,  H03F2203/45138 ,  H03F2203/45248 ,  H03F2203/45512 ,  H03H19/004

摘要： An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first amplifier stage (2) receiving the input signal, a second amplifier stage (3) driven by the first amplifier stage (2), and a third amplifier stage (4) driven by the second amplifier stage to produce the output signal. A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal (41) that operates a switch (MN0) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. The three stage amplifier can be a chopper-stabilized, notch-filtered amplifier.

摘要翻译： 运算放大器（1B）放大输入信号（Vin）以产生输出信号（Vout），并且包括一个包括接收输入信号的第一放大器级（2）和第二放大级（3）的三级放大器（1C） 由第一放大器级（2）驱动的第三放大级（4）和由第二放大级驱动的第三放大级（4）产生输出信号。 当输入信号（Vin）超过一定量值时，产生转换检测电流（Idetect），并转换成操作开关（MN0）的控制信号（41），使第一放大级的输出导体短路到 防止在回转期间与第一放大器级的输出相关联的电容上的信号电荷积聚。 三级放大器可以是斩波稳定的陷波滤波放大器。

公开(公告)号：US07292095B2

公开(公告)日：2007-11-06

申请号：US11340223

申请日：2006-01-26

申请人： Rodney T. Burt ,  Joy Y. Zhang

发明人： Rodney T. Burt ,  Joy Y. Zhang

IPC分类号： H03F1/02

CPC分类号： H03F3/45968 ,  H03F1/26 ,  H03F3/005 ,  H03F3/387 ,  H03F2200/261 ,  H03F2200/459 ,  H03F2203/45212 ,  H03H19/004 ,  H03H2011/0488

摘要： A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter filters the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment, a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

摘要翻译： 接收输入信号的斩波稳定放大器包括具有输入斩波器的第一操作跨导放大器和用于斩波由第一操作跨导放大器产生的输出信号的输出斩波器。 开关电容器陷波滤波器通过与输出斩波器的斩波频率同步工作来对斩波输出信号进行滤波，以滤除由输出斩波器产生的纹波电压。 在一个实施例中，第二运算跨导放大器放大陷波滤波器输出。 输入信号被前馈，与第二个运算跨导放大器的输出相加，并施加到第四个运算跨导放大器的输入端。 纹波噪声和偏移量大大降低。

公开(公告)号：US08072262B1

公开(公告)日：2011-12-06

申请号：US12803468

申请日：2010-06-28

申请人： Rodney T. Burt ,  Joy Y. Zhang

发明人： Rodney T. Burt ,  Joy Y. Zhang

IPC分类号： H03F1/02

CPC分类号： H03F3/005 ,  H03F3/38 ,  H03F2200/271

摘要： A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

摘要翻译： 斩波稳定电路（1）包括用于以第一频率斩波输入信号（Vin）的预斩波电路（26）以产生第一信号。 输入斩波电路（9）以基本上大于第一频率的第二频率斩波第一信号以产生第二信号。 第一频率是第二频率的次谐波。 斩波电路（30）以第一频率切断第二斩波信号以产生施加到信号调理电路（2）的输入的第三信号。 输出斩波电路（10）以第二频率斩波信号调理电路的输出，以产生第四信号。 第四个信号被滤波。

公开(公告)号：US20090278597A1

公开(公告)日：2009-11-12

申请号：US12151503

申请日：2008-05-07

申请人： Joy Y. Zhang ,  Viola Schaffer

发明人： Joy Y. Zhang ,  Viola Schaffer

IPC分类号： H03F1/02

CPC分类号： H03F3/005 ,  H03F3/387 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/408 ,  H03F2203/45138 ,  H03F2203/45248 ,  H03F2203/45512 ,  H03H19/004

摘要： An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first amplifier stage (2) receiving the input signal, a second amplifier stage (3) driven by the first amplifier stage (2), and a third amplifier stage (4) driven by the second amplifier stage to produce the output signal. A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal (41) that operates a switch (MN0) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. The three stage amplifier can be a chopper-stabilized, notch-filtered amplifier.

摘要翻译： 运算放大器（1B）放大输入信号（Vin）以产生输出信号（Vout），并且包括一个包括接收输入信号的第一放大器级（2）和第二放大级（3）的三级放大器（1C） 由第一放大器级（2）驱动的第三放大级（4）和由第二放大级驱动的第三放大级（4）产生输出信号。 当输入信号（Vin）超过一定量值时，产生转换检测电流（Idetect），并转换成操作开关（MN0）的控制信号（41），使第一放大级的输出导体短路到 防止在回转期间与第一放大器级的输出相关联的电容上的信号电荷积聚。 三级放大器可以是斩波稳定的陷波滤波放大器。

公开(公告)号：US07042290B2

公开(公告)日：2006-05-09

申请号：US10664311

申请日：2003-09-16

申请人： Joy Y. Zhang ,  Rodney T. Burt

发明人： Joy Y. Zhang ,  Rodney T. Burt

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F2203/45288 ,  H03F2203/45632 ,  H03F2203/45644 ,  H03F2203/45686

摘要： An output stage circuit is configured for enabling an output of an amplifier circuit to be pulled upwards and/or downwards to or beyond an upper power supply or below a lower power supply. The exemplary output stage circuit comprises a pair of output transistors configured to provide an output voltage, and a controlled resistive circuit. The controlled resistive element is configured to enhance the gain of the output stage circuit by modifying the dynamic impedance effect of the upper output transistor during pull-up operation, or the lower output transistor during pull-down operation. During normal operation, the controlled resistive element operates with low resistance, e.g., acts as a “short,” but during the pull-up or pull-down operation the controlled resistive element can be configured to add resistance to modify the dynamic impedance of the upper or lower output transistor. As a result, an amplifier circuit including an exemplary output stage circuit can swing towards or beyond an upper and/or lower power supply with minimal gain loss for the amplifier circuit, thus allowing for low voltage processes to be utilized.

摘要翻译： 输出级电路被配置为使得放大器电路的输出能够向上拉和/或向下拉到或超过上电源或低于较低电源。 示例性输出级电路包括被配置为提供输出电压的一对输出晶体管和受控电阻电路。 受控电阻元件被配置为通过在上拉操作期间修改上输出晶体管的动态阻抗效应或者在下拉操作期间降低输出晶体管来增强输出级电路的增益。 在正常操作期间，受控电阻元件以低电阻工作，例如充当“短路”，但是在上拉或下拉操作期间，受控电阻元件可被配置为增加电阻以修改 上或下输出晶体管。 结果，包括示例性输出级电路的放大器电路可以朝向或超出上部和/或下部电源摆动，对放大器电路具有最小的增益损耗，从而允许利用低电压工艺。

公开(公告)号：US20110316621A1

公开(公告)日：2011-12-29

申请号：US12803468

申请日：2010-06-28

申请人： Rodney T. Burt ,  Joy Y. Zhang

发明人： Rodney T. Burt ,  Joy Y. Zhang

IPC分类号： H03F1/02 ,  H03K17/00

CPC分类号： H03F3/005 ,  H03F3/38 ,  H03F2200/271

摘要： A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

摘要翻译： 斩波稳定电路（1）包括用于以第一频率斩波输入信号（Vin）的预斩波电路（26）以产生第一信号。 输入斩波电路（9）以基本上大于第一频率的第二频率斩波第一信号以产生第二信号。 第一频率是第二频率的次谐波。 斩波电路（30）以第一频率切断第二斩波信号以产生施加到信号调理电路（2）的输入的第三信号。 输出斩波电路（10）以第二频率斩波信号调理电路的输出，以产生第四信号。 第四个信号被滤波。

公开(公告)号：US07205833B2

公开(公告)日：2007-04-17

申请号：US10737419

申请日：2003-12-15

申请人： Rodney T. Burt ,  Joy Y. Zhang

发明人： Rodney T. Burt ,  Joy Y. Zhang

IPC分类号： H03F1/02

CPC分类号： H03F1/26 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2203/45174

摘要： An improved method and circuit for reduced settling time in an amplifier are provided. The amplifier comprises a composite amplifier circuit including a first amplifier configured with a second amplifier comprising an integrator circuit. The reduced settling time is facilitated through implementation of a faster path configured between an inverting input terminal of the second amplifier and an output terminal of the first amplifier for current needed by an integrator resistor due to any signal appearing at said inverting input terminal for said high-speed amplifier. The faster path can be realized through the addition of a compensation capacitor between the output terminal of the composite amplifier circuit and the inverting input terminal of the second amplifier. The compensation capacitor can comprise various values depending on any given number of design criteria. The additional path can also minimize the settling time effects from process variations in the various resistors and capacitors, as well as the amplifier gains, realized in the composite amplifier circuit.

摘要翻译： 提供了一种用于降低放大器稳定时间的方法和电路。 放大器包括复合放大器电路，其包括配置有包括积分器电路的第二放大器的第一放大器。 通过在第二放大器的反相输入端子和第一放大器的输出端子之间配置的较快路径，由于由所述反相输入端子出现的任何信号，由积分电阻器所需的电流来实现缩短的建立时间 速度放大器 可以通过在复合放大器电路的输出端子和第二放大器的反相输入端子之间添加补偿电容器来实现更快的路径。 补偿电容器可以包括根据任何给定数量的设计标准的各种值。 附加路径还可以最小化来自各种电阻器和电容器中的过程变化的稳定时间效应以及在复合放大器电路中实现的放大器增益。

公开(公告)号：US06897731B2

公开(公告)日：2005-05-24

申请号：US10693765

申请日：2003-10-24

申请人： Joy Y. Zhang ,  Rodney T. Burt

发明人： Joy Y. Zhang ,  Rodney T. Burt

IPC分类号： H03F1/08 ,  H03F1/52 ,  H02H7/20

CPC分类号： H03F1/523 ,  H03F1/086

摘要： A method and circuit for providing a faster overload recovery time for an amplifier circuit is provided. An overload recovery circuit is configured to reduce and/or eliminate the slow tail voltage that may be caused by overloading a composite amplifier, and thus provide a faster overload recovery time over a wide range of feedback components for the composite amplifier. The overload recovery circuit comprises a bypass device configured to provide a path for additional current to flow through during overload conditions, thus creating a “clamping” action with the feedback element of the amplifier circuit. As a result, the current flowing through the bypass device of the amplifier circuit will be large enough to hold an inverting node of the composite amplifier at the common mode voltage, thus reducing the overload recovery time. In addition, the overload recovery circuit can further comprise a stabilization circuit configured to stabilize the composite amplifier during overload condition by sensing when an overload condition is occurring, and modifying the feedback to the input terminals of the amplifier circuit to prevent oscillation.

摘要翻译： 提供了一种用于为放大器电路提供更快的过载恢复时间的方法和电路。 过载恢复电路被配置为减少和/或消除可能由复合放大器过载引起的慢尾电压，并且因此在复合放大器的广泛的反馈分量范围内提供更快的过载恢复时间。 过载恢复电路包括旁路装置，其被配置为在过载条件期间提供用于附加电流流过的路径，从而与放大器电路的反馈元件产生“钳位”动作。 结果，流过放大器电路的旁路装置的电流将足够大以将复合放大器的反相节点保持在共模电压，从而减少过载恢复时间。 此外，过载恢复电路还可以包括稳定电路，其被配置为在过载状态期间通过感测何时发生过载状况来稳定复合放大器，并且将反馈修改到放大器电路的输入端以防止振荡。

公开(公告)号：US07375585B2

公开(公告)日：2008-05-20

申请号：US11120088

申请日：2005-05-02

申请人： Dimitar T. Trifonov ,  Joy Y. Zhang

发明人： Dimitar T. Trifonov ,  Joy Y. Zhang

IPC分类号： H03F3/45

CPC分类号： H03F3/45219 ,  H03F2203/45424 ,  H03F2203/45504

摘要： An operational amplifier having a wide input common mode voltage range includes first (2) and second (3) differential input transistor pairs coupled to first (14) and second (15) tail current transistors. At least one of the first and second tail current transistor pairs is controlled by a common mode control circuit (4). A gate of the first tail current transistor (14) is coupled to the common mode control circuit (4) to turn the first tail current transistor on and to turn the second tail current transistor off when the common mode input voltage is below a common mode threshold voltage (CMTHR). A folded cascode stage (5) is driven by the first and second differential input transistor pairs. Switched active load transistors are coupled to active load transistors of the folded cascode stage and are operable in response to the common mode control circuit to divert part of a current produced by one of the first and second differential input pairs from the folded cascode circuit, depending on whether the common mode input voltage is above or below the common mode threshold voltage.

摘要翻译： 具有宽输入共模电压范围的运算放大器包括耦合到第一（14）和第二（15）尾电流晶体管的第一（2）和第二（3）差分输入晶体管对。 第一和第二尾电流晶体管对中的至少一个由共模控制电路（4）控制。 当共模输入电压低于公共模式时，第一尾电流晶体管（14）的栅极耦合到共模控制电路（4），以使第一尾电流晶体管导通并使第二尾电流晶体管截止， 阈值电压（CMTHR）。 折叠的共源共栅级（5）由第一和第二差分输入晶体管对驱动。 开关有源负载晶体管耦合到折叠共源共栅级的有源负载晶体管，并且响应于共模控制电路可操作以将部分由第一和第二差分输入对之一产生的电流从折叠共源共栅电路转移，这取决于 关于共模输入电压是否高于或低于共模阈值电压。