公开(公告)号：US20080109586A1

公开(公告)日：2008-05-08

申请号：US11594420

申请日：2006-11-08

申请人： Nitin Godiwala ,  Judson S. Leonard ,  Matthew H. Reilly

发明人： Nitin Godiwala ,  Judson S. Leonard ,  Matthew H. Reilly

IPC分类号： G06F13/14

CPC分类号： G06F13/1652

摘要： Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

摘要翻译： 用于虚拟通道仲裁的系统和方法，以防止富连接多处理器计算机系统中的活动锁定。 在多处理器计算机系统中防止了Livelock，其中大的多个处理节点中的每一个具有输入链路和出口链路。 分配虚拟通道来传达通信。 来自多个输入链路的通信数据被缓冲在交叉点缓冲器中。 交叉点缓冲区的一个子集为同一个出口链路的出价和仲裁使用。 识别所选通信的虚拟通道。 是否确定使用出口链路的任何其他通信招标是否与所识别的虚拟通道相关联，并且是否任何通信是否等待比选择的通信更长时间。 如果是这样，允许该通信在所选择的通信之前使用出口链路。

公开(公告)号：US20080109569A1

公开(公告)日：2008-05-08

申请号：US11594427

申请日：2006-11-08

申请人： Judson S. Leonard ,  Lawrence C. Stewart ,  David Gingold

发明人： Judson S. Leonard ,  Lawrence C. Stewart ,  David Gingold

IPC分类号： G06F13/28

CPC分类号： G06F15/16 ,  G06F12/0835 ,  G06F12/1081 ,  G06F2212/1016

摘要： The invention relates to a remote DMA system, and methods for supporting synchronization of distributed processes in a multiprocessor system using collective operations. One aspect of the invention is a multi-node computer system having a plurality of interconnected processing nodes. This system uses DMA engines to perform collective operations synchronizing processes executing on a set of nodes. Each process in the set of processes causes the DMA engine on the node on which the process executes, to transmit a collective operation command to the master node when the process reaches a synchronization point in its execution. The DMA engine on the master node receives and executes the collective operations from the processes, and in response to receiving a pre-established number of the collective operations, conditionally executing the set of associated commands.

摘要翻译： 本发明涉及一种远程DMA系统，以及用于支持使用集合操作的多处理器系统中的分布式进程的同步的方法。 本发明的一个方面是具有多个互连处理节点的多节点计算机系统。 该系统使用DMA引擎来执行在一组节点上执行的同步过程的集合操作。 当进程在其执行中达到同步点时，该组进程中的每个进程导致该进程执行的节点上的DMA引擎向主节点发送一个集体操作命令。 主节点上的DMA引擎从进程接收并执行集合操作，并且响应于接收到预先确定的集合操作数量，有条件地执行该组关联命令。

公开(公告)号：US20080107116A1

公开(公告)日：2008-05-08

申请号：US11594421

申请日：2006-11-08

申请人： Nitin Godiwala ,  Judson S. Leonard ,  Matthew H. Reilly ,  Lawrence C. Stewart

发明人： Nitin Godiwala ,  Judson S. Leonard ,  Matthew H. Reilly ,  Lawrence C. Stewart

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L1/00 ,  H04L1/1806 ,  H04L47/34 ,  H04L2001/0097

摘要： A large-scale multiprocessor system with a link-level interconnect that provides in-order packet delivery. The method comprises transmitting, over a link in the defined interconnection topology, a sequence of packets in a defined order from a first node to a second node. The second node is an intermediate node in a route between the first and third node. At the first node, the transmitted packets are stored in a buffer. In response to an error in reception, the first node retrieves packets from the buffer and re-transmits them to the second node, beginning with the packet subsequent to the last packet in the sequence correctly received by the second node and continuing through the remainder of the sequence of packets.

摘要翻译： 具有链路级互连的大规模多处理器系统，其提供按顺序的分组传送。 该方法包括通过所定义的互连拓扑中的链路，以从第一节点到第二节点的定义的顺序来传输分组序列。 第二节点是第一和第三节点之间的路由中的中间节点。 在第一个节点，传输的数据包被存储在一个缓冲器中。 响应于接收中的错误，第一节点从缓冲器检索分组并将其重新发送到第二节点，从在第二节点正确接收的序列中的最后一个分组之后的分组开始，并继续通过第二节点的剩余部分 数据包的顺序。

公开(公告)号：US20080107105A1

公开(公告)日：2008-05-08

申请号：US11594405

申请日：2006-11-08

申请人： Matthew H. Reilly ,  Nitin Godiwala ,  Judson S. Leonard

发明人： Matthew H. Reilly ,  Nitin Godiwala ,  Judson S. Leonard

IPC分类号： H04L12/56

CPC分类号： H04L49/9047 ,  H04L45/10 ,  H04L49/90

摘要： Systems and methods for communicating on a richly-connected multiprocessor computer system using a pool of buffers for dynamic association with a virtual channel. Packets are communicated in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology, in which a communication from a source processing node to a target processing node may pass through one or more intermediate nodes en route to the target processing node. A set of virtual channels is associated for each link in the interconnection topology. A first subset of buffers is dedicated for fixed correspondence to virtual channel identifiers, and a second subset of buffers is dedicated for dynamic allocation and assignment to virtual channels.

摘要翻译： 用于在富连接的多处理器计算机系统上进行通信的系统和方法，该缓冲区用于与虚拟通道动态关联。 分组在具有通过定义的互连拓扑互联的大量多个处理节点的多处理器计算机系统中通信，其中从源处理节点到目​​标处理节点的通信可以通过到目标处理的一个或多个中间节点 节点。 一组虚拟通道与互连拓扑中的每个链路相关联。 缓冲器的第一子集专用于对虚拟信道标识符的固定对应，并且第二子缓存器专用于动态分配和分配给虚拟信道。

公开(公告)号：US5113362A

公开(公告)日：1992-05-12

申请号：US521904

申请日：1990-05-11

申请人： Stephen W. Harston ,  Judson S. Leonard

发明人： Stephen W. Harston ,  Judson S. Leonard

IPC分类号： G06F17/17

CPC分类号： G06F17/17

摘要： An interpolator circuit is formed from a chain of multiplexer/adder circuits. Each multiplexer/adder circuit selects one of the two multi-bit binary values which are to be interpolated in accordance with one bit of a multi-bit ratio value. The selected value is shifted and added to the output of a previous stage in the chain. When one of the two values is injected into the first stage, the final sum generated by the circuit chain is the interpolated value.

摘要翻译： 内插器电路由多路复用器/加法器电路链形成。 每个多路复用器/加法器电路根据多比特率值的一个比特来选择待内插的两个多比特二进制值之一。 所选值被移位并添加到链中前一级的输出。 当两个值中的一个被注入到第一级时，由电路链产生的最终和是内插值。

公开(公告)号：US07773618B2

公开(公告)日：2010-08-10

申请号：US11594426

申请日：2006-11-08

申请人： Judson S. Leonard ,  Matthew H. Reilly ,  Nitin Godiwala

发明人： Judson S. Leonard ,  Matthew H. Reilly ,  Nitin Godiwala

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： G06F15/17381 ,  H04L47/10 ,  H04L47/11

摘要： Systems and methods for preventing deadlock in richly-connected multiprocessor computer system using dynamic assignment of virtual channels. Deadlock is prevented in a multiprocessor computer system having a large plurality of processing nodes interconnected by a defined interconnection topology. Each link in the interconnection topology is associated with a set of virtual channels. Each virtual channel has corresponding communication buffers to store communication data and each virtual channel has an associated virtual channel identifier. Each communication between a source processing node and a target processing node is assigned an initial virtual channel to convey the communication from the source processing node. At an intermediate processing node, a different virtual channel is assigned to convey the communication toward the target processing node, in accordance with pre-defined rules to avoid a cycle of dependency of communication buffer resources.

摘要翻译： 使用虚拟通道的动态分配来防止富连接多处理器计算机系统中的死锁的系统和方法。 在具有通过定义的互连拓扑互连的大量多个处理节点的多处理器计算机系统中，阻止了死锁。 互连拓扑中的每个链路与一组虚拟通道相关联。 每个虚拟通道具有对应的通信缓冲器以存储通信数据，并且每个虚拟通道具有相关联的虚拟通道标识符。 为源处理节点和目标处理节点之间的每个通信被分配初始虚拟通道以传送来自源处理节点的通信。 在中间处理节点处，分配不同的虚拟信道以根据预定义的规则向目标处理节点传送通信，以避免通信缓冲器资源的依赖循环。

公开(公告)号：US07773617B2

公开(公告)日：2010-08-10

申请号：US11594420

申请日：2006-11-08

申请人： Nitin Godiwala ,  Judson S. Leonard ,  Matthew H. Reilly

发明人： Nitin Godiwala ,  Judson S. Leonard ,  Matthew H. Reilly

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： G06F13/1652

摘要： Systems and methods for arbitrating for virtual channels to prevent livelock in richly-connected multiprocessor computer system. Livelock is prevented in a multiprocessor computer system, in which each of a large plurality processing node has input links and egress links. A virtual channel is assigned to convey the communication. Communication data from the plurality of input links is buffered in cross point buffers. A subset of the cross point buffers bids for, and arbitrates, use of the same one egress link. The virtual channel of the selected communication is identified. It is determined whether any of the other communications bidding for use of the egress link are associated with the identified virtual channel and if so whether any communication has been waiting longer than the selected communication. If so, allowing that communication to use the egress link before the selected communication does.

摘要翻译： 用于虚拟通道仲裁的系统和方法，以防止富连接多处理器计算机系统中的活动锁定。 在多处理器计算机系统中防止了Livelock，其中大的多个处理节点中的每一个具有输入链路和出口链路。 分配虚拟通道来传达通信。 来自多个输入链路的通信数据被缓冲在交叉点缓冲器中。 交叉点缓冲区的一个子集为同一个出口链路的出价和仲裁使用。 识别所选通信的虚拟通道。 是否确定使用出口链路的任何其他通信招标是否与所识别的虚拟通道相关联，并且是否任何通信是否等待比选择的通信更长时间。 如果是这样，允许该通信在所选择的通信之前使用出口链路。

公开(公告)号：US07533197B2

公开(公告)日：2009-05-12

申请号：US11594446

申请日：2006-11-08

申请人： Judson S. Leonard ,  David Gingold ,  Lawrence C. Stewart

发明人： Judson S. Leonard ,  David Gingold ,  Lawrence C. Stewart

IPC分类号： G06F13/28 ,  G06F15/167

CPC分类号： G06F13/28

摘要： A multi-node computer system with a plurality of interconnected processing nodes, including a method of using DMA engines without page locking by the operating system. The method includes a sending node with a first virtual address space and a receiving node with a second virtual address space. Performing a DMA data transfer operation between the first virtual address space on the sending node and the second virtual address space on the receiving node via a DMA engine, and if the DMA operation refers to a virtual address within the second virtual address space that is not in physical memory, causing the DMA operation to fail. The method includes causing the receiving node to map the referenced virtual address within the second virtual address space to a physical address, and causing the sending node to retry the DMA operation, wherein the retried DMA operation is performed without page locking.

摘要翻译： 一种具有多个互连处理节点的多节点计算机系统，包括不使用操作系统进行页锁定的DMA引擎的方法。 该方法包括具有第一虚拟地址空间的发送节点和具有第二虚拟地址空间的接收节点。 通过DMA引擎在发送节点上的第一虚拟地址空间和接收节点上的第二虚拟地址空间之间执行DMA数据传输操作，并且如果DMA操作涉及第二虚拟地址空间内的虚拟地址 在物理内存中，导致DMA操作失败。 该方法包括使得接收节点将第二虚拟地址空间内的被引用的虚拟地址映射到物理地址，并使得发送节点重试DMA操作，其中，在没有页面锁定的情况下执行重试的DMA操作。

公开(公告)号：US20080109570A1

公开(公告)日：2008-05-08

申请号：US11594446

申请日：2006-11-08

申请人： Judson S. Leonard ,  David Gingold ,  Lawrence C. Stewart

发明人： Judson S. Leonard ,  David Gingold ,  Lawrence C. Stewart

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Systems and methods for remote direct memory access without page locking by the operating system. A multi-node computer system has a plurality of interconnected processing nodes. DMA engines are used in a way to avoid page locking.

摘要翻译： 远程直接内存访问的系统和方法，无操作系统的页面锁定。 多节点计算机系统具有多个互连的处理节点。 DMA引擎用于避免页面锁定。

公开(公告)号：US4943915A

公开(公告)日：1990-07-24

申请号：US101984

申请日：1987-09-29

申请人： Neil C. Wilhelm ,  Judson S. Leonard

发明人： Neil C. Wilhelm ,  Judson S. Leonard

IPC分类号： G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/3885

摘要： In a data processing system with a central processing unit having a pipelined mode of operation, apparatus and method are disclosed for synchronizing the operation of a coprocessor unit with the remainder of the central processing unit, the remainder of the central processing unit being implemented for pipelined execution of instructions. Because the coprocessor unit performs manipulations of logic signal groups that require a longer time for execution than the manipulation contemplated by the requirements of pipelined instruction execution, the coprocessor unit must be synchronized with an instruction stream adapted to use the rigidly controlled pipelined implementation. In order to synchronize the coprocessor unit with the remainder of the central processing unit, the instructions controlling the operation of the coprocessor unit have two portions. A first portion of a coprocessor instruction designates the storage location into which the result of the previous operation is to be stored, while the second portion of the coprocessor instruction defines the operation to be performed on the operand in a designated location.

摘要翻译： 在具有流水线操作模式的中央处理单元的数据处理系统中，公开了用于使协处理器单元与中央处理单元的其余部分的操作同步的中间处理单元的其余部分被实施用于流水线 执行指令 由于协处理器单元执行逻辑信号组的操作，所述逻辑信号组需要比流水线指令执行的要求更长的执行时间，所以协处理器单元必须与适于使用刚性控制的流水线实现的指令流同步。 为了使协处理器单元与中央处理单元的其余部分同步，控制协处理器单元的操作的指令具有两部分。 协处理器指令的第一部分指定要存储先前操作的结果的存储位置，而协处理器指令的第二部分定义要在指定位置对操作数执行的操作。