公开(公告)号：US07966543B2

公开(公告)日：2011-06-21

申请号：US11741693

申请日：2007-04-27

申请人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： H03M13/00

CPC分类号： H03M13/1122 ,  H03M13/1117

摘要： A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×┌log2(k−1)┐ times to obtain k output results. Either of one first level sequences and one output results contains (k−1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×┌log2(k−1)┐ comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.

摘要翻译： 一种LDPC解码器的循环比较方法。 输入k个元素的第n个元素，其中n = 1。 。 。 ，k被相应的比较器顺序地去除以获得k个第一级序列。 接下来，使用从k个元素中选择的两个元素的对来形成k个第二等级序列。 上述步骤重复k×┌log2（k-1）┐次以获得k个输出结果。 一个第一级序列和一个输出结果中的任一个包含（k-1）个元素。 将第一级序列与输出结果进行比较，以确定它们是否相同。 如果它们相同，则该过程停止。 如果它们不相同，则重复上述步骤以获得新的输出结果。 本发明的循环比较方法只需要k×┌log2（k-1）┐比较来获得输出结果。 因此，本发明可以减少基本操作的数量并且可以应用于任何输入数。

公开(公告)号：US07945839B2

公开(公告)日：2011-05-17

申请号：US11742499

申请日：2007-04-30

申请人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： H03M13/00

CPC分类号： H03M13/1105 ,  H03M13/6502

摘要： The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

摘要翻译： 本发明公开了一种适用于CNU（校验节点单元）或VNU（可变节点单元）的LDPC（Low-Density Parity-Check）解码器的集合循环比较方法。 在本发明的系统化方法中，对所有输入元素进行初始化以获得矩阵。 基于矩阵的对称性，并且矩阵的行之间的相似度依次形成为不同的集合，分别对应于在水平和垂直方向上具有最大迭代次数的水平连续的元素，对称非连续非边界元素 ，边界元素加上同一行中的末端相邻元素。 本发明适用于任何输入号码。 通过比较集合之间的大交点，本发明可以有效地减少比较计算的数量，并大大提高LDPC解码器的性能。

公开(公告)号：US07773153B2

公开(公告)日：2010-08-10

申请号：US11316290

申请日：2005-12-22

申请人： Hsu-lin FanChiang ,  Jui-hung Hung ,  Hui-min Tsai

发明人： Hsu-lin FanChiang ,  Jui-hung Hung ,  Hui-min Tsai

IPC分类号： H04N9/475

CPC分类号： H04N9/44 ,  G09G5/008 ,  H04N5/126

摘要： A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator. The active pixel region generator receives an input vertical synchronous signal to generate a reference signal associated with an active pixel region. The frame-based phase-locked loop frame-based phase-locks the display enable signal to the reference signal.

摘要翻译： 描述了在显示系统中使用的基于帧的锁相显示控制器及其方法。 用于在视频信号中显示多个图像帧的基于帧的锁相显示控制器包括基于帧的锁相环和同步信号发生器。 基于帧的锁相环接收振荡信号和输入垂直同步信号，以通过基于帧的锁相环生成输出时钟信号。 耦合到基于帧的锁相环的同步信号发生器接收输出时钟信号以产生输出水平同步信号，输出垂直同步信号和输出显示使能（DE）信号。 基于帧的锁相环包括第一PLL，频率合成器，第二PLL，快速相位检测器，相位频率检测器和有源像素区域发生器。 有源像素区域发生器接收输入垂直同步信号以产生与有源像素区域相关联的参考信号。 基于帧的锁相环基于帧将显示使能信号锁定到参考信号。

公开(公告)号：US20070229422A1

公开(公告)日：2007-10-04

申请号：US11466933

申请日：2006-08-24

申请人： Jui-Hung Hung

发明人： Jui-Hung Hung

IPC分类号： G09G3/36

CPC分类号： G09G5/008 ,  G09G2300/0452

摘要： A control device is used with a delta panel of a display for processing and transmitting color data to be displayed on the delta panel according to a pixel clock received from the image processing circuit. A clock duplicating circuit of the control device processes said pixel clock into three clocks with respective frequency smaller than the frequency of the pixel clock. A clock adjusting device of the control device is coupled to the clock-duplicating circuit for processing the resulting three color clocks into a first color clock, a second color clock having a first phase difference from said first color clock, and a third color clock having a second phase difference from said second color clock, wherein the first color clock, the second color clock and the third color clock are output to the delta panel for sampling a first color data, a second color data and a third color data to the delta panel, respectively.

摘要翻译： 控制装置与显示器的三角形面板一起使用，用于根据从图像处理电路接收的像素时钟来处理和发送要显示在增量面板上的颜色数据。 控制装置的时钟复制电路将所述像素时钟处理成具有小于像素时钟的频率的相应频率的三个时钟。 控制装置的时钟调节装置被耦合到时钟复制电路，用于将所得到的三个颜色时钟处理成第一彩色时钟，具有与所述第一彩色时钟的第一相位差的第二彩色时钟和第三彩色时钟具有 与所述第二颜色时钟的第二相位差，其中所述第一颜色时钟，所述第二颜色时钟和所述第三颜色时钟被输出到所述增量面板，用于将第一颜色数据，第二颜色数据和第三颜色数据采样到所述三角形 面板。

公开(公告)号：US20060170823A1

公开(公告)日：2006-08-03

申请号：US11316290

申请日：2005-12-22

申请人： Hsu-lin FanChiang ,  Jui-hung Hung ,  Hui-min Tsai

发明人： Hsu-lin FanChiang ,  Jui-hung Hung ,  Hui-min Tsai

IPC分类号： H04N9/475

CPC分类号： H04N9/44 ,  G09G5/008 ,  H04N5/126

摘要： A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator. The active pixel region generator receives an input vertical synchronous signal to generate a reference signal associated with an active pixel region. The frame-based phase-locked loop frame-based phase-locks the display enable signal to the reference signal.

摘要翻译： 描述了在显示系统中使用的基于帧的锁相显示控制器及其方法。 用于在视频信号中显示多个图像帧的基于帧的锁相显示控制器包括基于帧的锁相环和同步信号发生器。 基于帧的锁相环接收振荡信号和输入垂直同步信号，以通过基于帧的锁相环生成输出时钟信号。 耦合到基于帧的锁相环的同步信号发生器接收输出时钟信号以产生输出水平同步信号，输出垂直同步信号和输出显示使能（DE）信号。 基于帧的锁相环包括第一PLL，频率合成器，第二PLL，快速相位检测器，相位频率检测器和有源像素区域发生器。 有源像素区域发生器接收输入垂直同步信号以产生与有源像素区域相关联的参考信号。 基于帧的锁相环基于帧将显示使能信号锁定到参考信号。

公开(公告)号：US07274371B2

公开(公告)日：2007-09-25

申请号：US10906741

申请日：2005-03-03

申请人： Kun-Nan Cheng ,  Jui-Hung Hung

发明人： Kun-Nan Cheng ,  Jui-Hung Hung

IPC分类号： G09G5/36 ,  G06T1/60

CPC分类号： G09G3/3611 ,  G09G2370/04

摘要： A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-playing device. The control circuit can store the control parameters via the FIFO to the memory first, and then transfer the control parameters stored in the memory via the FIFO to the register during a synchronizing blank period.

摘要翻译： 数据播放控制器包括用于存储多个控制参数的寄存器，用于存储数据的先进先出缓冲器（FIFO）以及能够动态访问存储器的控制电路。 寄存器可以电连接到数据播放设备。 控制电路可以先通过FIFO将控制参数存储到存储器中，然后在同步空白期间通过FIFO将存储在存储器中的控制参数传送到寄存器。

公开(公告)号：US20050195204A1

公开(公告)日：2005-09-08

申请号：US10906741

申请日：2005-03-03

申请人： KUN-NAN CHENG ,  JUI-HUNG HUNG

发明人： KUN-NAN CHENG ,  JUI-HUNG HUNG

IPC分类号： G06F13/00 ,  G09G5/00 ,  G09G5/22 ,  G09G5/36 ,  G09G5/37

CPC分类号： G09G3/3611 ,  G09G2370/04

摘要： A data-playing controller includes a register for storing a plurality of control parameters, a first-in-first-out buffer (FIFO) for storing data, and a control circuit capable of accessing a memory dynamically. The register can be electrically connected to a data-playing device. The control circuit can store the control parameters via the FIFO to the memory first, and then transfer the control parameters stored in the memory via the FIFO to the register during a synchronizing blank period.

摘要翻译： 数据播放控制器包括用于存储多个控制参数的寄存器，用于存储数据的先进先出缓冲器（FIFO）以及能够动态访问存储器的控制电路。 寄存器可以电连接到数据播放设备。 控制电路可以先通过FIFO将控制参数存储到存储器中，然后在同步空白期间通过FIFO将存储在存储器中的控制参数传送到寄存器。

公开(公告)号：US20080244336A1

公开(公告)日：2008-10-02

申请号：US11742499

申请日：2007-04-30

申请人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： G06K5/04

CPC分类号： H03M13/1105 ,  H03M13/6502

摘要： The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

摘要翻译： 本发明公开了一种适用于CNU（校验节点单元）或VNU（可变节点单元）的LDPC（Low-Density Parity-Check）解码器的集合循环比较方法。 在本发明的系统化方法中，对所有输入元素进行初始化以获得矩阵。 基于矩阵的对称性，并且矩阵的行之间的相似度依次形成为不同的集合，分别对应于在水平和垂直方向上具有最大迭代次数的水平连续的元素，对称非连续非边界元素 ，边界元素加上同一行中的末端相邻元素。 本发明适用于任何输入号码。 通过比较集合之间的大交点，本发明可以有效地减少比较计算的数量，并大大提高LDPC解码器的性能。

公开(公告)号：US20080222499A1

公开(公告)日：2008-09-11

申请号：US11741693

申请日：2007-04-27

申请人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： H03M13/09

CPC分类号： H03M13/1122 ,  H03M13/1117

摘要： The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log2(k−1) times to obtain k completion series. Either of one first series and one completion series contains (k−1) elements. The first series are compared with the completion series to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new completion series. The cyclic comparison method of the present invention needs only k×log2(k−1) comparisons to obtain completion series. Thus, the present invention can reduce the number of basic operations and can apply to any input number. Further, the present invention can be easily programmed and can achieve the optimal solution.

摘要翻译： 本发明公开了一种适用于LDPC解码器中使用的比较器的LDPC解码器的循环比较方法。 根据本发明的循环比较算法，输入k个元素的第n个元素，其中n = 1，...。 。 。 ，k被相应的比较器顺序地去除以获得k个第一系列。 接下来，使用从k个元素中选择的两个元素的对来形成k个第二系列。 上述步骤重复kxlog2（k-1）次以获得k个完成序列。 一个第一个序列和一个完成序列中的任一个包含（k-1）个元素。 将第一个系列与完成系列进行比较，以确定它们是否相同。 如果它们相同，则该过程停止。 如果不相同，则重复上述步骤以获得新的完成系列。 本发明的循环比较方法仅需要kxlog2（k-1）比较以获得完成序列。 因此，本发明可以减少基本操作的数量并且可以应用于任何输入数。 此外，本发明可以容易地编程并且可以实现最佳解决方案。