公开(公告)号：US20080244336A1

公开(公告)日：2008-10-02

申请号：US11742499

申请日：2007-04-30

申请人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： G06K5/04

CPC分类号： H03M13/1105 ,  H03M13/6502

摘要： The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

摘要翻译： 本发明公开了一种适用于CNU（校验节点单元）或VNU（可变节点单元）的LDPC（Low-Density Parity-Check）解码器的集合循环比较方法。 在本发明的系统化方法中，对所有输入元素进行初始化以获得矩阵。 基于矩阵的对称性，并且矩阵的行之间的相似度依次形成为不同的集合，分别对应于在水平和垂直方向上具有最大迭代次数的水平连续的元素，对称非连续非边界元素 ，边界元素加上同一行中的末端相邻元素。 本发明适用于任何输入号码。 通过比较集合之间的大交点，本发明可以有效地减少比较计算的数量，并大大提高LDPC解码器的性能。

公开(公告)号：US07966543B2

公开(公告)日：2011-06-21

申请号：US11741693

申请日：2007-04-27

申请人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： H03M13/00

CPC分类号： H03M13/1122 ,  H03M13/1117

摘要： A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×┌log2(k−1)┐ times to obtain k output results. Either of one first level sequences and one output results contains (k−1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×┌log2(k−1)┐ comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.

摘要翻译： 一种LDPC解码器的循环比较方法。 输入k个元素的第n个元素，其中n = 1。 。 。 ，k被相应的比较器顺序地去除以获得k个第一级序列。 接下来，使用从k个元素中选择的两个元素的对来形成k个第二等级序列。 上述步骤重复k×┌log2（k-1）┐次以获得k个输出结果。 一个第一级序列和一个输出结果中的任一个包含（k-1）个元素。 将第一级序列与输出结果进行比较，以确定它们是否相同。 如果它们相同，则该过程停止。 如果它们不相同，则重复上述步骤以获得新的输出结果。 本发明的循环比较方法只需要k×┌log2（k-1）┐比较来获得输出结果。 因此，本发明可以减少基本操作的数量并且可以应用于任何输入数。

公开(公告)号：US07945839B2

公开(公告)日：2011-05-17

申请号：US11742499

申请日：2007-04-30

申请人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui Hung ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： H03M13/00

CPC分类号： H03M13/1105 ,  H03M13/6502

摘要： The present invention discloses a set-cyclic comparison method for an LDPC (Low-Density Parity-Check) decoder, which applies to a CNU (Check Node Unit) or a VNU (Variable Node Unit). In the systematized method of the present invention, all the input elements are initialized to obtain a matrix. Based on the symmetry of the matrix and the similarity between the rows of the matrix are sequentially formed different sets respectively corresponding to the horizontally-continuous elements having the maximum iteration number in the horizontal and vertical directions, the symmetric non-continuous non-boundary elements, and the boundary elements plus the end-around neighboring elements in the same row. The present invention applies to any input number. Via the large intersection between the compared sets, the present invention can effectively reduce the number of comparison calculations and greatly promote the performance of an LDPC decoder.

摘要翻译： 本发明公开了一种适用于CNU（校验节点单元）或VNU（可变节点单元）的LDPC（Low-Density Parity-Check）解码器的集合循环比较方法。 在本发明的系统化方法中，对所有输入元素进行初始化以获得矩阵。 基于矩阵的对称性，并且矩阵的行之间的相似度依次形成为不同的集合，分别对应于在水平和垂直方向上具有最大迭代次数的水平连续的元素，对称非连续非边界元素 ，边界元素加上同一行中的末端相邻元素。 本发明适用于任何输入号码。 通过比较集合之间的大交点，本发明可以有效地减少比较计算的数量，并大大提高LDPC解码器的性能。

公开(公告)号：US20080222499A1

公开(公告)日：2008-09-11

申请号：US11741693

申请日：2007-04-27

申请人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

发明人： Jui-Hui HUNG ,  Jui-Hung Hung ,  Sau-Gee Chen

IPC分类号： H03M13/09

CPC分类号： H03M13/1122 ,  H03M13/1117

摘要： The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first series. Next, pairs of two elements selected from the k elements are used to form k second series. The preceding step is repeated k×log2(k−1) times to obtain k completion series. Either of one first series and one completion series contains (k−1) elements. The first series are compared with the completion series to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new completion series. The cyclic comparison method of the present invention needs only k×log2(k−1) comparisons to obtain completion series. Thus, the present invention can reduce the number of basic operations and can apply to any input number. Further, the present invention can be easily programmed and can achieve the optimal solution.

摘要翻译： 本发明公开了一种适用于LDPC解码器中使用的比较器的LDPC解码器的循环比较方法。 根据本发明的循环比较算法，输入k个元素的第n个元素，其中n = 1，...。 。 。 ，k被相应的比较器顺序地去除以获得k个第一系列。 接下来，使用从k个元素中选择的两个元素的对来形成k个第二系列。 上述步骤重复kxlog2（k-1）次以获得k个完成序列。 一个第一个序列和一个完成序列中的任一个包含（k-1）个元素。 将第一个系列与完成系列进行比较，以确定它们是否相同。 如果它们相同，则该过程停止。 如果不相同，则重复上述步骤以获得新的完成系列。 本发明的循环比较方法仅需要kxlog2（k-1）比较以获得完成序列。 因此，本发明可以减少基本操作的数量并且可以应用于任何输入数。 此外，本发明可以容易地编程并且可以实现最佳解决方案。

公开(公告)号：US5430669A

公开(公告)日：1995-07-04

申请号：US162498

申请日：1993-12-03

申请人： Sau-Gee Chen ,  Chieh-Chih Li

发明人： Sau-Gee Chen ,  Chieh-Chih Li

IPC分类号： G06F7/552 ,  G06F7/38

CPC分类号： G06F7/5525

摘要： A fast square root method which separates the sign detection operation of the remainder from the remainder subtraction operation. By taking the absolute values of the remainders, the method can successively subtract the remainder without knowing the signs of remainders, while signs of the remainder can be detected in parallel fashion and independently. The method also uses a smaller square root digit set of {-1, 1} than {-1, 0, 1} that is used by many known fast algorithms. This digit set facilitates fast conversion of the results to binary representations. Together with some hardware design techniques, the square root method can be realized and pipelined in simple circuits.

摘要翻译： 一种快速平方根法，将余数的符号检测操作与余数减法运算相分离。 通过取余数的绝对值，该方法可以连续减去余数，而不知道余数的符号，而余下的符号可以以并行方式独立地检测。 该方法还使用许多已知快速算法使用的比{-1，0,1}更小的平方根数字组{-1，1}。 该数字集有助于将结果快速转换为二进制表示。 连同一些硬件设计技术，平方根方法可以在简单的电路中实现和流水线化。

公开(公告)号：US07516172B1

公开(公告)日：2009-04-07

申请号：US08510740

申请日：1995-08-02

申请人： Sau-Gee Chen ,  Chieh-Chih Li

发明人： Sau-Gee Chen ,  Chieh-Chih Li

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F7/4824 ,  G06F2207/5352

摘要： A fast division method which uses a smaller quotient digit set of {−1, 1} than {−1, 0, 1} that is used by known algorithms, therefore accelerates the speed of calculation. Partial remainders can be computed with the signals of remainders decided independently and in parallel. By taking the absolute values of the remainders, we can successively subtract the remainders without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The algorithm adopts non-restoring division operation and CSA type of operation for fast subtraction. The algorithm is also an on-line algorithm that facilitates highly pipelined operation while it is much simpler than the existing on-line algorithms.

摘要翻译： 使用由已知算法使用的比{-1，0,1}更小的{1,1}的商数字组的快速分割方法因此加快了计算速度。 可以用独立且并行确定的余数的信号来计算部分余数。 以剩余物的绝对价值为依据，我们可以连续减去剩余物，而不需要知道剩余物的迹象，而剩余物的迹象可以同时并行独立地决定。 该算法采用非恢复分割操作和CSA操作类型进行快速减法。 该算法也是一种在线算法，它有助于高度流水线运算，而且比现有的在线算法简单得多。

公开(公告)号：US5416733A

公开(公告)日：1995-05-16

申请号：US188053

申请日：1994-01-26

申请人： Sau-Gee Chen ,  Chieh-Chih Li

发明人： Sau-Gee Chen ,  Chieh-Chih Li

IPC分类号： G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5352

摘要： A fast divider is disclosed in the present invention. It utilizes a division method which uses a smaller quotient digit set of {-1, 1} than {-1, 0, 1} that used by known algorithms, therefore accelerates the speed of calculation. Partial remainders are computed with the signs of remainders decided independently and in parallel. By taking the absolute values of the remainders, the remainders are successively subtracted without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The method adopts non-restoring division operation and CSA (carry save adder) type of operation for fast subtraction. The method is also an on-line algorithm that facilitates highly pipelined operations while it is much simpler than the existing on-line algorithms.

摘要翻译： 在本发明中公开了一种快速分离器。 它利用一种使用已知算法使用的比{-1，0,1}更小的{1,1}的商数集合的除法，从而加速计算速度。 计算剩余部分的独立和并行决定的余数。 依靠剩余部分的绝对值，连续减去余数，不需要知道余数的迹象，而剩余部分的符号可以同时并行独立地决定。 该方法采用非恢复分割操作和CSA（进位保存加法器）操作类型进行快速减法。 该方法也是一种在线算法，它有助于高度流水线化的操作，同时它比现有的在线算法简单得多。

公开(公告)号：US08218665B2

公开(公告)日：2012-07-10

申请号：US12003690

申请日：2007-12-31

申请人： Wen-Long Chin ,  Sau-Gee Chen

发明人： Wen-Long Chin ,  Sau-Gee Chen

IPC分类号： H04L5/12

CPC分类号： H04L27/2662 ,  H04L27/2657

摘要： A symbol time synchronization method for OFDM systems is disclosed. The invention presents a joint maximum-likelihood (ML) synchronization method for symbol time offset (STO) in OFDM systems. The method is developed in frequency domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of symbol time offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. The joint estimation's method is robust, because it exhibits high performances in high mobility and time-variant multipath fading channels.

摘要翻译： 公开了OFDM系统的符号时间同步方法。 本发明提供OFDM系统中符号时间偏移（STO）的联合最大似然（ML）同步方法。 该方法在时域多径信道下在频域开发。 通过分析接收的频域数据，推导出符号时间偏移（STO），载波频率偏移（CFO）和采样时钟频率偏移（SCFO）的共同作用的数学模型。 结果用于制定两个连续符号的对数似然函数。 联合估计的方法是鲁棒的，因为它在高移动性和时变多径衰落信道中表现出高性能。

公开(公告)号：US20090028042A1

公开(公告)日：2009-01-29

申请号：US12003690

申请日：2007-12-31

申请人： Wen-Long Chin ,  Sau-Gee Chen

发明人： Wen-Long Chin ,  Sau-Gee Chen

IPC分类号： H04J11/00 ,  H04L27/28

CPC分类号： H04L27/2662 ,  H04L27/2657

摘要： A symbol time synchronization method for OFDM systems is disclosed. The invention presents a joint maximum-likelihood (ML) synchronization method for symbol time offset (STO) for OFDM systems. The method is developed in frequency-domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of symbol time offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. The joint estimation's method is robust, because it exhibits high performances in high mobility and time-variant multipath fading channels.

摘要翻译： 公开了OFDM系统的符号时间同步方法。 本发明提出了OFDM系统的符号时间偏移（STO）的联合最大似然（ML）同步方法。 该方法在时域多径信道下在频域上开发。 通过分析接收的频域数据，推导出符号时间偏移（STO），载波频率偏移（CFO）和采样时钟频率偏移（SCFO）的共同作用的数学模型。 结果用于制定两个连续符号的对数似然函数。 联合估计的方法是鲁棒的，因为它在高移动性和时变多径衰落信道中表现出高性能。

公开(公告)号：US5832442A

公开(公告)日：1998-11-03

申请号：US493970

申请日：1995-06-23

申请人： Gang-Janp Lin ,  Sau-Gee Chen ,  Der-Chwan Wu ,  Yuan-An Kao ,  Yen-Hui Wang

发明人： Gang-Janp Lin ,  Sau-Gee Chen ,  Der-Chwan Wu ,  Yuan-An Kao ,  Yen-Hui Wang

IPC分类号： G10H7/00 ,  G01L9/08

CPC分类号： G10H7/008

摘要： A method is disclosed of modification of parameters of audio signals by dividing a digital signal converted from an original analog signal into sound frames, modifying a pitch and a playing rate of the digital signal within a frame and subsequent successive splicing a last modified frame with a first non-modified frame and calculating the mean absolute error to define the best splicing point in terms of producing minimal or no audible noise such that various sections of sound signals can be spliced together to achieve pitch and playing rate modification. An apparatus is also disclosed for implementing the method, the apparatus comprising input and output amplifiers, a low pass filter at the input and a low pass filter at the output, analog-to-digital and digital-to-analog converters, and a pitch shifting processor.

摘要翻译： 公开了一种通过将从原始模拟信号转换成的数字信号分成声音帧来修改音频信号的参数的方法，修改帧内的数字信号的音调和播放速率，并且随后使用 第一非修改帧并计算平均绝对误差，以便在产生最小或不可听到的噪声方面定义最佳拼接点，使得声音信号的各个部分可以拼接在一起以实现音调和播放速率修改。 还公开了一种用于实现该方法的装置，该装置包括输入和输出放大器，输入端的低通滤波器和输出模数转换器和数/模转换器之间的低通滤波器，以及间距 移位处理器