公开(公告)号：US5706422A

公开(公告)日：1998-01-06

申请号：US682012

申请日：1996-07-16

Applicant: Hisayuki Maruyama ,  Jushi Ide ,  Seiichi Yasumoto ,  Sadao Mizokawa ,  Ken Onuki ,  Toshio Ishihara ,  Masato Satake ,  Toshihiko Uchiyama

Inventor： Hisayuki Maruyama ,  Jushi Ide ,  Seiichi Yasumoto ,  Sadao Mizokawa ,  Ken Onuki ,  Toshio Ishihara ,  Masato Satake ,  Toshihiko Uchiyama

IPC: G06F11/00 ,  H04L12/42 ,  H04L12/437

CPC classification number: G06F11/1479 ,  H04L12/437 ,  G06F11/1489

Abstract: A plurality of different fault locating functions are provided in a communication system comprising a plurality of terminals connected to a data transmission channel. The functions are at different levels, respectively, ranging from a level for rapid fault location to a level for reliable and sure fault location. Upon detection of an occurrence of a fault, one fault locating function is performed. If the fault is not located accurately located, another fault locating function of a level for more reliable is performed, thus the functions are performed sequentially in the order from the level for rapid location to the level for more deliberate and reliable location. Preferably, the channel is reconfigured to avoid the fault, according to the fault located by the functions of the respective levels. With this arrangement, a fault which does most possibly occur can be located quickly, while another fault difficult to locate can be located accurately.

Abstract translation: 在包括连接到数据传输信道的多个终端的通信系统中提供多个不同的故障定位功能。 这些功能分别处于不同的级别，从快速故障定位的级别到可靠和可靠的故障定位的级别。 在检测到故障发生时，执行一个故障定位功能。 如果故障定位不准确，则可以进行更可靠的故障定位功能，从而可以按照从快速到高级的顺序顺序执行功能，从而更有效，可靠的位置。 优选地，根据由各个级别的功能定位的故障，重新配置信道以避免故障。 通过这种布置，可能发生最可能发生的故障可以快速定位，而难以定位的另一个故障可以准确定位。

公开(公告)号：US5003458A

公开(公告)日：1991-03-26

申请号：US111618

申请日：1987-10-23

Applicant: Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

Inventor： Shinichiro Yamaguchi ,  Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hirokazu Hirayama ,  Takayuki Morioka ,  Soichi Takaya ,  Yukio Kawamoto ,  Jushi Ide ,  Yoshihiro Miyazaki

IPC: G06F11/14

CPC classification number: G06F11/141

Abstract: Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Abstract translation: 在微程序控制数据处理装置中进行指令重新开始处理的方法和装置，其中，在指令暂停之后重启指令执行时，指令执行暂停时的数据处理装置的内部信息被保存在存储器中，之后 暂停原因清除过程执行保存的内部信息被恢复。 根据微程序的指定，存储与当前执行的微程序地址相关联的检查点地址。 暂停之后，执行删除处理，指令的执行使用检查点地址重新开始。 如果在暂停原因移除处理被执行之后没有存储检查点地址，则从主存储器的暂停指令的读取操作重新开始指令的执行。

公开(公告)号：US4783731A

公开(公告)日：1988-11-08

申请号：US030266

申请日：1987-03-24

Applicant: Yoshihiro Miyazaki ,  Jushi Ide ,  Takeshi Kato ,  Hiroaki Nakanishi ,  Tadaaki Bandoh

Inventor： Yoshihiro Miyazaki ,  Jushi Ide ,  Takeshi Kato ,  Hiroaki Nakanishi ,  Tadaaki Bandoh

IPC: G06F12/16 ,  G06F9/46 ,  G06F11/36 ,  G06F12/14 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/00

CPC classification number: G06F11/3648 ,  G06F9/468

Abstract: A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.

Abstract translation: 具有双公共存储器的多计算机系统，其中在公共存储器内设置指定的地址区域。 无论CPU处于在线模式还是调试模式，指定的地址区都可以访问，而只有当公用存储器的功能模式与访问模式一致时，除指定地址区域之外的任何区域才可访问 中央处理器。 对应于每个CPU，由CPU使用的地址被划分为多组地址，并且为各个地址组设置访问模式。

公开(公告)号：US4200865A

公开(公告)日：1980-04-29

申请号：US872794

申请日：1978-01-27

Applicant: Takayuki Morioka ,  Jushi Ide

Inventor： Takayuki Morioka ,  Jushi Ide

IPC: G06F1/18 ,  G06F13/40 ,  H05K1/11 ,  H05K1/04

CPC classification number: G06F13/4081 ,  H01R23/68 ,  H05K1/117 ,  H05K2201/0746

Abstract: A printed circuit board loaded with an electronic circuit and constructed to be capable of being inserted in and withdrawn from a bus line on on-line status, in which the input to or the output from the printed circuit board is locked out in response to the presence of two conditions, one is the presence of a demand for insertion or withdrawal of the printed circuit board on on-line status and the other is the presence of such a condition that no information exchange is being made between the printed circuit board and other unit connected with the bus line, thereby releasing the electrical connection between the bus line and the printed circuit board so that the printed circuit board can now be inserted in or withdrawn from the bus line on on-line status.

Abstract translation: 一种印刷电路板，其装有电子电路并被构造成能够在线上状态下从总线插入和取出，其中响应于所述印刷电路板的输入或从印刷电路板的输出被锁定 存在两种情况，一种是在线状态下存在对印刷电路板的插入或取出的需求，另一种是存在这样的情况，即在印刷电路板和其它电路板之间不进行信息交换 单元与总线连接，从而释放总线与印刷电路板之间的电气连接，使得印刷电路板现在可以在线状态插入总线或从总线上取出。

公开(公告)号：US4918561A

公开(公告)日：1990-04-17

申请号：US254224

申请日：1988-10-06

Applicant: Hiroshi Watanabe ,  Yoshiaki Takahashi ,  Masayuki Sakata ,  Koshirou Adachi ,  Jushi Ide ,  Atsuo Yoshida

Inventor： Hiroshi Watanabe ,  Yoshiaki Takahashi ,  Masayuki Sakata ,  Koshirou Adachi ,  Jushi Ide ,  Atsuo Yoshida

IPC: G10K11/16 ,  H05K7/20

CPC classification number: H05K7/20136

Abstract: A housing for accomodating an electronic apparatus including heat-generating parts, in which the surface of a cooling air inlet port in the front or rear side of the housing is formed in arcuate fashion and recessed as viewed from the interior of the housing. As a result, the velocity of air introduced is remarkably reduced thereby improving the heat radiation of the housing.

Abstract translation: 一种用于容纳包括发热部件的电子设备的壳体，其中壳体的前侧或后侧中的冷却空气入口的表面形成为弓形并且从壳体的内部观察时凹陷。 结果，引入的空气的速度显着降低，从而改善了壳体的散热。

公开(公告)号：US4766590A

公开(公告)日：1988-08-23

申请号：US792319

申请日：1985-10-28

Applicant: Takuji Hamada ,  Masahiro Takahashi ,  Kotaro Hirasawa ,  Jushi Ide ,  Hitoshi Fushimi ,  Seiichi Yasumoto

Inventor： Takuji Hamada ,  Masahiro Takahashi ,  Kotaro Hirasawa ,  Jushi Ide ,  Hitoshi Fushimi ,  Seiichi Yasumoto

IPC: H04L12/42 ,  H04Q11/00 ,  H04J3/00

CPC classification number: H04L12/42

Abstract: A loop transmission system having a plurality of data processor connected through respective transmission station with a common loop transmission line is disclosed. This system has a concentrator connected with a plurality of transmission stations through respective loop transmission lines. The concentrator changes the order of connection said loop transmission lines thereby to change the order of connected of said transmission stations on said loop transmission lines.

Abstract translation: 公开了一种具有多个数据处理器的环路传输系统，该多个数据处理器通过相应的传输站与公共环路传输线相连。 该系统具有通过各个环路传输线与多个发送站连接的集中器。 集中器改变所述环路传输线路连接的顺序，从而改变所述环路传输线上所述传输站的连接顺序。

公开(公告)号：US4638308A

公开(公告)日：1987-01-20

申请号：US654390

申请日：1984-09-26

Applicant: Hiroshi Kuwabara ,  Jushi Ide ,  Yasuji Kamata ,  Kenkichi Yamashita

Inventor： Hiroshi Kuwabara ,  Jushi Ide ,  Yasuji Kamata ,  Kenkichi Yamashita

IPC: H04N3/00 ,  G09G1/04 ,  G09G1/16 ,  H03K4/02 ,  H03K4/06 ,  G09G1/08

CPC classification number: H03K4/06 ,  G09G1/04 ,  H03K4/026

Abstract: A CRT picture display apparatus of the raster scan type comprises a cathode ray tube for raster scanning, a horizontal deflection circuit for supplying a horizontal deflection current to a horizontal deflection coil of the CRT, a vertical deflection circuit for supplying a vertical deflection current to a vertical deflection coil of the CRT, and a display data generator for supplying data to be displayed to the CRT. The horizontal deflection circuit produces as the horizontal deflection current a triangular current having one period which is twice a horizontal scanning period, and the triangular current has a first portion which increases in response to a horizontal sync signal at a predetermined inclination and a second portion which decreases in response to the next horizontal sync signal at the predetermined inclination and continues until the further next horizontal sync signal, whereby the period for a scanning line to proceed from lefthand end to righthand end of a raster on a screen of the CRT is made substantially equal to the period for the next scanning line to proceed from righthand end to lefthand end, and data is displayed during both the periods.

Abstract translation: 光栅扫描型的CRT图像显示装置包括用于光栅扫描的阴极射线管，用于向CRT的水平偏转线圈提供水平偏转电流的水平偏转电路，用于向垂直偏转电流提供垂直偏转电流的垂直偏转电路 CRT的垂直偏转线圈和用于提供要显示给CRT的数据的显示数据发生器。 水平偏转电路作为水平偏转电流产生具有水平扫描周期的两倍的一个周期的三角形电流，并且三角形电流具有响应于预定倾斜度的水平同步信号而增加的第一部分和第二部分， 以预定的倾斜度响应于下一个水平同步信号而减小并且持续到下一个下一个水平同步信号，由此基本上使扫描线从CRT的屏幕上的光栅的左端到右端进行的周期 等于下一个扫描线从右端到左端的时间段，并在两个时间段内显示数据。

公开(公告)号：US4497035A

公开(公告)日：1985-01-29

申请号：US337292

申请日：1982-01-05

Applicant: Shigeru Yabuuchi ,  Takeyuki Endoh ,  Kazuyuki Kodama ,  Jushi Ide

Inventor： Shigeru Yabuuchi ,  Takeyuki Endoh ,  Kazuyuki Kodama ,  Jushi Ide

IPC: G06F7/64 ,  G06F17/13 ,  G06F17/17 ,  H03H17/00 ,  H03H17/02 ,  H03H17/08 ,  G06F15/32 ,  G06J1/02

CPC classification number: G06F17/13 ,  G06F7/64

Abstract: In order to deliver an input signal of each operation cycle after a desired time delay, there are disposed data memory means for storing the input signal, counter means for appointing write addresses of the data memory means, and address memory means for appointing read addresses of the data memory means. The address memory means is divided into partial memory areas equal in number to time delay elements, whereupon while sampling the input signal at a predetermined sampling period and changing the count value of the counter means one by one for each of the desired time delay elements at each sampling point, the variations of the input signal in a sampling interval between the particular sampling point and the adjacent sampling point are successively written into the memory means. Further, while changing the contents of the partial memory areas corresponding to the desired time delay element to the number of the time delay elements in each sampling interval, the variations in a sampling interval preceding a predetermined sampling number to the particular sampling interval are successively read out from the memory means. The input signal of each operation cycle in the preceding sampling interval is presumed by an interpolation operation based on the variation and the sampling period, and the result is used as an output signal of the desired time delay element.

Abstract translation: 为了在期望的时间延迟之后传送每个操作周期的输入信号，存在用于存储输入信号的数据存储装置，用于指定数据存储装置的写地址的计数器装置，以及用于指定数据存储装置的读地址的地址存储装置 数据存储装置。 地址存储器装置被分成数量等于时间延迟元件的部分存储器区域，然后在预定的采样周期对输入信号进行采样，并且针对每个期望的时间延迟元件逐个改变计数器装置的计数值 每个采样点，特定采样点和相邻采样点之间的采样间隔中的输入信号的变化被连续地写入存储装置。 此外，在将每个采样间隔中的期望时间延迟元件的部分存储器区域的内容改变为时间延迟元件的数量的同时，依次读取预定采样数之前的采样间隔与特定采样间隔的变化 从记忆的方式出来。 在前一采样间隔中的每个操作周期的输入信号由基于变化和采样周期的内插操作推测，并且该结果被用作期望的时间延迟元件的输出信号。

公开(公告)号：US4853890A

公开(公告)日：1989-08-01

申请号：US485396

申请日：1983-04-15

Applicant: Shigeo Abe ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Jushi Ide

Inventor： Shigeo Abe ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Jushi Ide

IPC: G06F7/00 ,  G06F9/30 ,  G06F15/16 ,  G06F15/167 ,  G06F15/78 ,  G06F17/16

CPC classification number: G06F9/30134 ,  G06F15/8084 ,  G06F9/30112

Abstract: In a vector processor including pipeline processors and means for synchronously controlling each component, there is provided an FIFO memory for temporarily storing the output of each pipeline processor and for outputting the stored data, in the order of storing, to at least one of the pipeline processors. Since intermediate result of operation is temporarily stored in the FIFO memory, a simple microprogram can be used and thus the capacity of the memory for microprogram can be reduced even if the successive intermediate results for calculation of vector elements are overlapped within the loop of the microprogram.

Abstract translation: 在包括流水线处理器的矢量处理器和用于同步控制每个组件的装置中，提供了一个FIFO存储器，用于临时存储每个流水线处理器的输出，并按存储顺序将存储的数据输出到至少一个流水线 处理器。 由于中间操作结果被临时存储在FIFO存储器中，所以可以使用简单的微程序，因此即使用于向量元素的计算的连续中间结果重叠在微程序循环内，微程序存储器的容量也可以减小 。

公开(公告)号：US4530050A

公开(公告)日：1985-07-16

申请号：US408924

申请日：1982-08-17

Applicant: Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

Inventor： Yasushi Fukunaga ,  Tadaaki Bandoh ,  Kotaro Hirasawa ,  Hidekazu Matsumoto ,  Jushi Ide ,  Takeshi Katoh ,  Hiroaki Nakanishi ,  Tetsuya Kawakami ,  Ryosei Hiraoka

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/36

CPC classification number: G06F9/30167 ,  G06F9/30152 ,  G06F9/3016

Abstract: A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

Abstract translation: 一种用于执行可变长度指令的中央处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的种类和操作数的操作码无关。 每个操作数说明符由一个或多个数据字节形成，并且具有指示特定操作数说明符是否是最后一个操作数说明符的停止位标志。 通过添加停止位标志，可以共享操作数说明符，可以使用相同的操作码执行不同的处理。 在操作码解码装置提供指示最后一个操作数的输出的情况下，在对应的操作数说明符中没有检测到停止位平面，相应的指令被检测为错误。