公开(公告)号：US06631060B2

公开(公告)日：2003-10-07

申请号：US09726923

申请日：2000-11-30

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

IPC分类号： H02H900

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L29/0626

摘要： A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region. The FOD may additionally include one or more n+ regions at the respective boundaries of the drain-side and source-side n+ diffusion regions to provide improved junction curvature. In addition to the field oxide interposed between the drain-side and source-side n+ diffusion regions, field oxides can be added respectively at the drain and source ends to provide isolation from other devices within an integrated circuit.

公开(公告)号：US08224637B1

公开(公告)日：2012-07-17

申请号：US11732194

申请日：2007-04-02

申请人： Jane W. Sowards ,  Shuxian Wu ,  Kaiman Chan

发明人： Jane W. Sowards ,  Shuxian Wu ,  Kaiman Chan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.

摘要翻译： 本发明的一个方面涉及对集成电路设计中的晶体管进行建模。 获得集成电路设计的布局数据。 从布局数据中提取将晶体管与至少一个注入井的至少一个阱边缘相关联的几何形状。 基于使用互补误差函数的至少一个阱边缘来计算晶体管的有效阱接近值。 晶体管使用有效的阱接近值进行建模。 在一个实施例中，将有效阱接近值添加到用于集成电路设计的后布局提取的网表。 可以使用后布局提取的网表来模拟集成电路设计。 在模拟集成电路的步骤期间，可以使用有效阱接近度来计算晶体管的阈值电压。