公开(公告)号：US06631060B2

公开(公告)日：2003-10-07

申请号：US09726923

申请日：2000-11-30

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

IPC分类号： H02H900

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L29/0626

摘要： A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region. The FOD may additionally include one or more n+ regions at the respective boundaries of the drain-side and source-side n+ diffusion regions to provide improved junction curvature. In addition to the field oxide interposed between the drain-side and source-side n+ diffusion regions, field oxides can be added respectively at the drain and source ends to provide isolation from other devices within an integrated circuit.

公开(公告)号：US06492231B2

公开(公告)日：2002-12-10

申请号：US09881245

申请日：2001-06-08

申请人： Chun-Mai Liu ,  Kung-Yen Su ,  Kai-Man Chan ,  Albert V. Kordesch

发明人： Chun-Mai Liu ,  Kung-Yen Su ,  Kai-Man Chan ,  Albert V. Kordesch

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

摘要翻译： 公开了一种用于制造三重自对准非易失性存储器件的方法。 该方法包括在衬底上形成隔离氧化物。 通过将第一多晶硅层沉积并自对准到隔离氧化物来形成多个浮栅。 然后在浮动栅极之间的衬底上限定公共源极区域。 第二多晶硅层沉积在公共源区上并相对于隔离氧化物自对准。 第三多晶硅层沉积在多个浮动栅极附近。 然后通过将第三多晶硅层自对准到隔离氧化物来形成多个选择栅极。 此外，在衬底上限定至少一个漏极区域。

公开(公告)号：US5959883A

公开(公告)日：1999-09-28

申请号：US4798

申请日：1998-01-09

申请人： James Brennan, Jr. ,  Anthony Dunne ,  Peter Holzmann ,  Geoff Jackson ,  Albert Kordesch ,  Chun-Mai Liu ,  Kung-Yen Su ,  Hieu Van Tran

发明人： James Brennan, Jr. ,  Anthony Dunne ,  Peter Holzmann ,  Geoff Jackson ,  Albert Kordesch ,  Chun-Mai Liu ,  Kung-Yen Su ,  Hieu Van Tran

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C27/00 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C16/30 ,  G11C2207/16 ,  G11C2211/5623

摘要： An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.

摘要翻译： 使用非易失性闪存的模拟录音和播放系统。 闪存单元阵列用于存储模拟信号，并实时检索存储的模拟信号。 多个列驱动器电路耦合到闪存单元的列，用于同时编程和读取。 使用编程算法将模拟信号写入闪存单元的工作范围内，因为工作范围可能由于工艺变化而偏移。 该系统包括三角电路，以提供可调整的初始编程电压，编程步骤，编程电流，读取电流和选择栅极电压。 该系统还包括与主机微控制器连接的串行外设接口（“SPI”）。 主机微控制器可以通过SPI向系统发送多个命令，以实现高效的消息管理。 这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。 该系统利用行和列冗余来提高产量。

公开(公告)号：US06493199B1

公开(公告)日：2002-12-10

申请号：US09697928

申请日：2000-10-26

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Wei-Fan Chen

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Wei-Fan Chen

IPC分类号： H02H900

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p+ and n+ doped regions for cathode connection formed within the n-doped well, and spaced-apart p+ and n+ doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n+ doped region and the n-well. The vertical zener junction has a p+ doped region sandwiched between two n+ doped regions. The n+ doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well. The SCR may further include respective field oxides between the anode p+ and n+ doped regions, between the anode n+ doped region and the vertical zener junction, and between the vertical zener junction and the n-doped well. Also provided is an n-doped substrate version of the SCR. The SCR with the vertical zener junction is characterized as having a relatively low breakdown voltage, having improved current handling capability for more reliable and robust operations, and having a breakdown voltage dependent on the doping concentration of the lighter doped p+ or n+ doped region of the vertical zener junction.

摘要翻译： 用作静电放电（ESD）保护装置的可控硅整流器（SCR），具有用于触发击穿的垂直齐纳结。 SCR包括具有n掺杂阱的p掺杂衬底，用于阴极连接的间隔开的p +和n +掺杂区域，形成在n掺杂阱内，并且间隔开的p +和n +掺杂区域用于与p形成的阳极连接 在n-掺杂阱外部的衬底。 SCR还包括位于阳极n +掺杂区域和n-阱之间的垂直齐纳点。 垂直齐纳结具有夹在两个n +掺杂区之间的p +掺杂区。 最靠近n-阱的垂直齐纳点的n +掺杂区域可以至少部分地在n阱内延伸，或者完全在n阱之外。 SCR可以进一步包括在阳极p +和n +掺杂区域之间，阳极n +掺杂区域和垂直齐纳结之间以及垂直齐纳结和n掺杂阱之间的相应场氧化物。 还提供了SCR的n掺杂衬底版本。 具有垂直齐纳结的SCR具有相对较低的击穿电压，具有改进的电流处理能力，用于更可靠和鲁棒的操作，并且具有取决于较轻掺杂的p +或n +掺杂区域的掺杂浓度的击穿电压 垂直齐纳结。

公开(公告)号：US06563733B2

公开(公告)日：2003-05-13

申请号：US09866537

申请日：2001-05-24

申请人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

发明人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

IPC分类号： G11C1604

CPC分类号： H01L29/511 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.

摘要翻译： 半导体存储器包括沿行和列布置的多个存储单元，每个单元具有浮置栅极，漏极区域，源极区域，程序栅极端子和选择栅极端子。 沿着每行单元的单元的程序栅极端子连接在一起形成连续的程序栅极线。 沿着每行单元的单元的选择栅极端子连接在一起形成连续的选择栅极线。 沿着每行单元格的单元格的源区域连接在一起形成连续的源极线。 沿着每列的单元被分成预定数量的组，并且每个组中的单元的漏极区域连接到跨越单元组中的单元格延伸的局部位线。 全局位线沿着每两列单元格延伸，并且被配置为选择性地提供沿着相应的两列单元格的本地位线的电连接。 每个单元的浮置栅极来自第一层多晶硅，编程栅极线来自第二多晶硅层，选择栅极线来自第三多晶硅层，源极线是扩散线。

公开(公告)号：US06922046B2

公开(公告)日：2005-07-26

申请号：US10817220

申请日：2004-04-02

申请人： Chun-Mai Liu ,  Hagop A. Nazarian

发明人： Chun-Mai Liu ,  Hagop A. Nazarian

IPC分类号： H03G1/00 ,  H03H7/24 ,  H02J3/12

CPC分类号： H03H7/24 ,  H03G1/0088

摘要： An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

摘要翻译： 阻抗网络。 网络包括多个阻抗元件，至少一个端子端子和擦拭器端子。 网络还包括第一多个开关元件，其选择性地向至少一个端子端子提供抽头位置，可在多个阻抗元件中的阻抗元件的第一规定增量处选择。 网络还包括第二多个开关元件，其选择性地提供抽头位置到抽头端子，可选择在多个阻抗元件中的阻抗元件的第二规定增量。

公开(公告)号：US06489200B1

公开(公告)日：2002-12-03

申请号：US09613495

申请日：2000-07-11

申请人： Len-Yi Leu ,  Chun-Mai Liu ,  Ken Su ,  Albert V. Kordesch

发明人： Len-Yi Leu ,  Chun-Mai Liu ,  Ken Su ,  Albert V. Kordesch

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/3144 ,  H01L27/0629 ,  H01L27/115 ,  H01L28/40

摘要： A method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.

摘要翻译： 在衬底上形成电容器的方法包括形成覆盖衬底的第一多晶硅层以限定浮动栅极。 形成覆盖第一多晶硅层的第二多晶硅以限定电容器的控制栅极和第一电极。 在第二多晶硅层上形成电介质层。 在电介质层上形成第三多晶硅层。 蚀刻第三多晶硅层以限定电容器的第二电极。 此后，蚀刻介电层。

公开(公告)号：US07038297B2

公开(公告)日：2006-05-02

申请号：US10761890

申请日：2004-01-21

申请人： Paul Vande Voorde ,  Chun-Mai Liu

发明人： Paul Vande Voorde ,  Chun-Mai Liu

IPC分类号： H01L29/00

CPC分类号： H01L29/8605 ,  Y10S257/904

摘要： Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C.Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

摘要翻译： 离子注入电阻器形成在晶体硅基体的主体中。 电阻器具有与硅衬底不同的导电类型。 电阻层的薄层电阻和温度依赖性由植入物的剂量决定。 温度变化可以在-40℃至+ 85℃的温度范围内优化为小于2％。此外，室温（〜25℃）下的温度变化可以降低到接近零。

公开(公告)号：US06744244B2

公开(公告)日：2004-06-01

申请号：US10114375

申请日：2002-04-01

申请人： Chun-Mai Liu ,  Hagop A. Nazarian

发明人： Chun-Mai Liu ,  Hagop A. Nazarian

IPC分类号： H02J312

CPC分类号： H03H7/24 ,  H03G1/0088

摘要： An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.

公开(公告)号：US06301151B1

公开(公告)日：2001-10-09

申请号：US09634180

申请日：2000-08-09

申请人： Lawrence D. Engh ,  Albert V. Kordesch ,  Ping Guo ,  Chun-Mai Liu

发明人： Lawrence D. Engh ,  Albert V. Kordesch ,  Ping Guo ,  Chun-Mai Liu

IPC分类号： G11C700

CPC分类号： G11C16/12 ,  G11C27/005

摘要： Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is “adaptive” because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells. Because of the programming speed of the exemplary method, a voice signal may be sampled and stored in flash memory one cell at a time. Variable programming parameters other than voltage may be used if desired.

摘要翻译： 闪存模拟存储的自适应编程方法和装置。 本发明的方法是基于先前脉冲的结果每次调节编程脉冲的电压。 将编程值的预期变化与测量的变化进行比较，以及用于在每个编程脉冲之后改善该单元的模型的差异。 该算法是“自适应”的，因为每个脉冲的电压适应于任何单元需要。 如果电池的编程速度太慢，电压会急剧增加，使其更快。 相反，如果结果显示特定的单元格编程速度太快，则下一个电压脉冲仅增加少量（或者如果需要甚至减小）。 由于单元的响应是非线性的，所以使用特殊的模拟电路来计算每个脉冲的最佳电压。 作为一种替代方案，也可以使用数字计算来对单元进行编程。 由于示例性方法的编程速度，一次可以将语音信号采样并存储在闪存中一个单元。 如果需要，可以使用电压以外的可变编程参数。