公开(公告)号：US06631060B2

公开(公告)日：2003-10-07

申请号：US09726923

申请日：2000-11-30

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

IPC分类号： H02H900

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L29/0626

摘要： A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region. The FOD may additionally include one or more n+ regions at the respective boundaries of the drain-side and source-side n+ diffusion regions to provide improved junction curvature. In addition to the field oxide interposed between the drain-side and source-side n+ diffusion regions, field oxides can be added respectively at the drain and source ends to provide isolation from other devices within an integrated circuit.

公开(公告)号：US06493199B1

公开(公告)日：2002-12-10

申请号：US09697928

申请日：2000-10-26

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Wei-Fan Chen

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Wei-Fan Chen

IPC分类号： H02H900

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p+ and n+ doped regions for cathode connection formed within the n-doped well, and spaced-apart p+ and n+ doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n+ doped region and the n-well. The vertical zener junction has a p+ doped region sandwiched between two n+ doped regions. The n+ doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well. The SCR may further include respective field oxides between the anode p+ and n+ doped regions, between the anode n+ doped region and the vertical zener junction, and between the vertical zener junction and the n-doped well. Also provided is an n-doped substrate version of the SCR. The SCR with the vertical zener junction is characterized as having a relatively low breakdown voltage, having improved current handling capability for more reliable and robust operations, and having a breakdown voltage dependent on the doping concentration of the lighter doped p+ or n+ doped region of the vertical zener junction.

摘要翻译： 用作静电放电（ESD）保护装置的可控硅整流器（SCR），具有用于触发击穿的垂直齐纳结。 SCR包括具有n掺杂阱的p掺杂衬底，用于阴极连接的间隔开的p +和n +掺杂区域，形成在n掺杂阱内，并且间隔开的p +和n +掺杂区域用于与p形成的阳极连接 在n-掺杂阱外部的衬底。 SCR还包括位于阳极n +掺杂区域和n-阱之间的垂直齐纳点。 垂直齐纳结具有夹在两个n +掺杂区之间的p +掺杂区。 最靠近n-阱的垂直齐纳点的n +掺杂区域可以至少部分地在n阱内延伸，或者完全在n阱之外。 SCR可以进一步包括在阳极p +和n +掺杂区域之间，阳极n +掺杂区域和垂直齐纳结之间以及垂直齐纳结和n掺杂阱之间的相应场氧化物。 还提供了SCR的n掺杂衬底版本。 具有垂直齐纳结的SCR具有相对较低的击穿电压，具有改进的电流处理能力，用于更可靠和鲁棒的操作，并且具有取决于较轻掺杂的p +或n +掺杂区域的掺杂浓度的击穿电压 垂直齐纳结。

公开(公告)号：US20090309182A1

公开(公告)日：2009-12-17

申请号：US12140195

申请日：2008-06-16

申请人： Kung-Yen Su ,  Yaw Wen Hu ,  Bomy Chen ,  Kevin Gene-Wah Jew

发明人： Kung-Yen Su ,  Yaw Wen Hu ,  Bomy Chen ,  Kevin Gene-Wah Jew

IPC分类号： H01L23/62

CPC分类号： H01L27/0259

摘要： A first embodiment of an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region. In a second embodiment, a well of a second conductivity type is provided in the substrate of the first conductivity type. The well has a top surface. A first region of the second conductivity type is near the top surface. A second region of the second conductivity type is in the well, substantially along the bottom of the well. A third region of the first conductivity type, is immediately adjacent to and in contact with the second region, substantially beneath the second region. A fourth region of the first conductivity type is in the well, along the top surface thereof, and spaced apart from the first region. The first region and the fourth region receive the ESD signal.

摘要翻译： 用于保护集成电路免受ESD信号的集成电路的静电放电（ESD）结构的第一实施例具有第一导电类型的衬底。 衬底具有顶表面。 第二导电类型的第一区域靠近顶表面并接收ESD信号。 第二导电类型的第二区域在基板中，在基本上垂直的方向上与第一区域分离并间隔开。 第一导电类型的第三区域，其浓度比衬底更重，与第二区域紧邻并与第二区域接触，基本上在第二区域下方。 在第二实施例中，在第一导电类型的衬底中提供第二导电类型的阱。 井有顶面。 第二导电类型的第一区域靠近顶表面。 第二导电类型的第二区域在井中，基本上沿着井的底部。 第一导电类型的第三区域紧邻第二区域并与第二区域接触，基本上在第二区域下方。 第一导电类型的第四区域沿着其顶表面位于阱中并与第一区域间隔开。 第一区域和第四区域接收ESD信号。

公开(公告)号：US5959883A

公开(公告)日：1999-09-28

申请号：US4798

申请日：1998-01-09

申请人： James Brennan, Jr. ,  Anthony Dunne ,  Peter Holzmann ,  Geoff Jackson ,  Albert Kordesch ,  Chun-Mai Liu ,  Kung-Yen Su ,  Hieu Van Tran

发明人： James Brennan, Jr. ,  Anthony Dunne ,  Peter Holzmann ,  Geoff Jackson ,  Albert Kordesch ,  Chun-Mai Liu ,  Kung-Yen Su ,  Hieu Van Tran

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C27/00 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C16/30 ,  G11C2207/16 ,  G11C2211/5623

摘要： An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options. The system utilizes row and column redundancy to increase production yield.

摘要翻译： 使用非易失性闪存的模拟录音和播放系统。 闪存单元阵列用于存储模拟信号，并实时检索存储的模拟信号。 多个列驱动器电路耦合到闪存单元的列，用于同时编程和读取。 使用编程算法将模拟信号写入闪存单元的工作范围内，因为工作范围可能由于工艺变化而偏移。 该系统包括三角电路，以提供可调整的初始编程电压，编程步骤，编程电流，读取电流和选择栅极电压。 该系统还包括与主机微控制器连接的串行外设接口（“SPI”）。 主机微控制器可以通过SPI向系统发送多个命令，以实现高效的消息管理。 这些命令包括记录或回放的基本命令以及各种寻址和消息提示选项。 该系统利用行和列冗余来提高产量。

公开(公告)号：US06492231B2

公开(公告)日：2002-12-10

申请号：US09881245

申请日：2001-06-08

申请人： Chun-Mai Liu ,  Kung-Yen Su ,  Kai-Man Chan ,  Albert V. Kordesch

发明人： Chun-Mai Liu ,  Kung-Yen Su ,  Kai-Man Chan ,  Albert V. Kordesch

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

摘要翻译： 公开了一种用于制造三重自对准非易失性存储器件的方法。 该方法包括在衬底上形成隔离氧化物。 通过将第一多晶硅层沉积并自对准到隔离氧化物来形成多个浮栅。 然后在浮动栅极之间的衬底上限定公共源极区域。 第二多晶硅层沉积在公共源区上并相对于隔离氧化物自对准。 第三多晶硅层沉积在多个浮动栅极附近。 然后通过将第三多晶硅层自对准到隔离氧化物来形成多个选择栅极。 此外，在衬底上限定至少一个漏极区域。