公开(公告)号：US06563733B2

公开(公告)日：2003-05-13

申请号：US09866537

申请日：2001-05-24

申请人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

发明人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

IPC分类号： G11C1604

CPC分类号： H01L29/511 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells. The floating gate of each cell is from a first layer polysilicon, the program gate lines are from a second polysilicon layer, the select gate lines are from a third polysilicon layer, and the source lines are diffusion lines.

摘要翻译： 半导体存储器包括沿行和列布置的多个存储单元，每个单元具有浮置栅极，漏极区域，源极区域，程序栅极端子和选择栅极端子。 沿着每行单元的单元的程序栅极端子连接在一起形成连续的程序栅极线。 沿着每行单元的单元的选择栅极端子连接在一起形成连续的选择栅极线。 沿着每行单元格的单元格的源区域连接在一起形成连续的源极线。 沿着每列的单元被分成预定数量的组，并且每个组中的单元的漏极区域连接到跨越单元组中的单元格延伸的局部位线。 全局位线沿着每两列单元格延伸，并且被配置为选择性地提供沿着相应的两列单元格的本地位线的电连接。 每个单元的浮置栅极来自第一层多晶硅，编程栅极线来自第二多晶硅层，选择栅极线来自第三多晶硅层，源极线是扩散线。

公开(公告)号：US08626580B2

公开(公告)日：2014-01-07

申请号：US11468896

申请日：2006-08-31

申请人： Sheng-Chi Chin ,  Shouh-Dauh Fred Lin ,  Lawrence Chen ,  Chun-Mai Liu ,  Huang-Sheng Lin

发明人： Sheng-Chi Chin ,  Shouh-Dauh Fred Lin ,  Lawrence Chen ,  Chun-Mai Liu ,  Huang-Sheng Lin

IPC分类号： G06Q30/00 ,  G06Q30/02

CPC分类号： G06Q30/0207 ,  G06Q30/02 ,  G06Q30/0217 ,  G06Q30/0235

摘要： A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

摘要翻译： 半导体优惠券服务系统包括用于管理半导体服务的息票服务模块; 与半导体服务相关的优惠券发生器，用于生成与半导体服务相关联的优惠券; 以及与半导体服务相关的息票维护者，用于处理与优惠券相关联的优惠券操作。

公开(公告)号：US06716700B2

公开(公告)日：2004-04-06

申请号：US10421020

申请日：2003-04-21

申请人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

发明人： Chun-Mai Liu ,  Albert Kordesch ,  Ming-Bing Chang

IPC分类号： H01L21336

CPC分类号： H01L29/511 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

摘要翻译： 形成具有行和列的存储器单元的半导体存储器的方法如下： 从第二层多晶硅形成多行编程栅极线; 从第三多晶硅层形成多行选择栅极线; 形成多行扩散源线：从第一层金属形成多个局部位线，沿着每列的单元被划分成预定数量的组，并且每组中的单元的漏极连接到 局部位线延伸穿过细胞组中的细胞; 以及从沿着每个单元的两列延伸的第二层金属形成多个全局位线，每个全局位线被配置为选择性地提供沿相应的两列单元格的本地位线的电连接。

公开(公告)号：US06709943B2

公开(公告)日：2004-03-23

申请号：US10228231

申请日：2002-08-26

申请人： Paul Vande Voorde ,  Chun-Mai Liu

发明人： Paul Vande Voorde ,  Chun-Mai Liu

IPC分类号： H01L2702

CPC分类号： H01L29/8605 ,  Y10S257/904

摘要： Ion implanted resistors formed in the body of a crystalline silicon substrate. The resistors have a different conductivity type from that of the silicon substrate. The sheet resistance and temperature dependence of the resistor layer is determined by the dose of the implant. Temperature variation can be optimized to be less than 2% over the temperature range −40 C to +85 C. Furthermore, the temperature variation at room temperature (˜25 C) can be reduced to nearly zero.

摘要翻译： 离子注入电阻器形成在晶体硅基体的主体中。 电阻器具有与硅衬底不同的导电类型。 电阻层的薄层电阻和温度依赖性由植入物的剂量决定。 温度变化可以在-40℃至+ 85℃的温度范围内优化为小于2％。此外，室温（〜25℃）下的温度变化可以降低到接近零。

公开(公告)号：US06631060B2

公开(公告)日：2003-10-07

申请号：US09726923

申请日：2000-11-30

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Kaiman Chan

IPC分类号： H02H900

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L29/0626

摘要： A field oxide device (FOD) useful for electrostatic discharge (ESD) protection and other applications. The FOD is characterized as being capable of achieving a relatively low breakdown voltage and capable of handling relatively high currents during an ESD event. In general, the FOD includes a zener junction to promote an earlier breakdown of the device. The zener junction also provides a planar-like breakdown region which makes it capable of handling relatively high currents. In particular, the FOD includes a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The FOD further includes a p+ doped region that interfaces with the drain-side n+ diffusion region to form a zener junction. The breakdown voltage of the FOD can be easily set by controlling the doping concentration and energy of the p+ doped region. The FOD may additionally include one or more n+ regions at the respective boundaries of the drain-side and source-side n+ diffusion regions to provide improved junction curvature. In addition to the field oxide interposed between the drain-side and source-side n+ diffusion regions, field oxides can be added respectively at the drain and source ends to provide isolation from other devices within an integrated circuit.

公开(公告)号：US06493199B1

公开(公告)日：2002-12-10

申请号：US09697928

申请日：2000-10-26

申请人： Kung-Yen Su ,  Chun-Mai Liu ,  Wei-Fan Chen

发明人： Kung-Yen Su ,  Chun-Mai Liu ,  Wei-Fan Chen

IPC分类号： H02H900

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p+ and n+ doped regions for cathode connection formed within the n-doped well, and spaced-apart p+ and n+ doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n+ doped region and the n-well. The vertical zener junction has a p+ doped region sandwiched between two n+ doped regions. The n+ doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well. The SCR may further include respective field oxides between the anode p+ and n+ doped regions, between the anode n+ doped region and the vertical zener junction, and between the vertical zener junction and the n-doped well. Also provided is an n-doped substrate version of the SCR. The SCR with the vertical zener junction is characterized as having a relatively low breakdown voltage, having improved current handling capability for more reliable and robust operations, and having a breakdown voltage dependent on the doping concentration of the lighter doped p+ or n+ doped region of the vertical zener junction.

摘要翻译： 用作静电放电（ESD）保护装置的可控硅整流器（SCR），具有用于触发击穿的垂直齐纳结。 SCR包括具有n掺杂阱的p掺杂衬底，用于阴极连接的间隔开的p +和n +掺杂区域，形成在n掺杂阱内，并且间隔开的p +和n +掺杂区域用于与p形成的阳极连接 在n-掺杂阱外部的衬底。 SCR还包括位于阳极n +掺杂区域和n-阱之间的垂直齐纳点。 垂直齐纳结具有夹在两个n +掺杂区之间的p +掺杂区。 最靠近n-阱的垂直齐纳点的n +掺杂区域可以至少部分地在n阱内延伸，或者完全在n阱之外。 SCR可以进一步包括在阳极p +和n +掺杂区域之间，阳极n +掺杂区域和垂直齐纳结之间以及垂直齐纳结和n掺杂阱之间的相应场氧化物。 还提供了SCR的n掺杂衬底版本。 具有垂直齐纳结的SCR具有相对较低的击穿电压，具有改进的电流处理能力，用于更可靠和鲁棒的操作，并且具有取决于较轻掺杂的p +或n +掺杂区域的掺杂浓度的击穿电压 垂直齐纳结。

公开(公告)号：US5903041A

公开(公告)日：1999-05-11

申请号：US263920

申请日：1994-06-21

申请人： Michael David La Fleur ,  Ralph Whitten ,  Chun-Mai Liu ,  Alan E. Comer ,  Scott Graham ,  Yu-Lin Lee

发明人： Michael David La Fleur ,  Ralph Whitten ,  Chun-Mai Liu ,  Alan E. Comer ,  Scott Graham ,  Yu-Lin Lee

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L29/04 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002

摘要： A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive. An improvement permitting higher current programming of B-fuses either alone or as part of Ab-fuse structures, incorporates an air gap which provides a pocket of space either above, below or both above and below the B-fuse portion of the device. This air gap provides a place for material disrupted (melted or vaporized) by a fuse or Ab-fuse programming event to go, eliminates direct contact between the dielectric material and the fuse-portion of the device, and also thermally isolates the melted fuse material from the dielectric, thus reducing the physical stress within the dielectric itself associated with high current programming and avoiding undesired collateral damage normally associated with high current programming events. The creation of an air gap around the fuse neck is accomplished by the removal of a sacrificial layer of an oxidizable polymer material in a gaseous and/or plasma state through a small hole in the dielectric referred to as a sacrificial via opening or just "sacrificial via". After removal of the oxidizable polymer material through the sacrificial via, the sacrificial via is sealed with a passivation layer formed of a polymeric material to prevent damage to the underlying structure. The integration of the air gap and sacrificial via sealing into the current fuse process manufacturing requires the following additional processing steps: (1) Air gap definition; (2) Air gap evacuation with oxygen plasma; (3) the application of the sealing polymer; and (4) the curing of the sealing polymer.

公开(公告)号：US20070156526A1

公开(公告)日：2007-07-05

申请号：US11468896

申请日：2006-08-31

申请人： Sheng-Chi CHIN ,  Shouh-Dauh Fred LIN ,  Lawrence CHEN ,  Chun-Mai LIU ,  Huang-Sheng LIN

发明人： Sheng-Chi CHIN ,  Shouh-Dauh Fred LIN ,  Lawrence CHEN ,  Chun-Mai LIU ,  Huang-Sheng LIN

IPC分类号： G06Q30/00

CPC分类号： G06Q30/0207 ,  G06Q30/02 ,  G06Q30/0217 ,  G06Q30/0235

摘要： A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

摘要翻译： 半导体优惠券服务系统包括用于管理半导体服务的息票服务模块; 与半导体服务相关的优惠券发生器，用于生成与半导体服务相关联的优惠券; 以及与半导体服务相关的息票维护者，用于处理与优惠券相关联的优惠券操作。

公开(公告)号：US06492231B2

公开(公告)日：2002-12-10

申请号：US09881245

申请日：2001-06-08

申请人： Chun-Mai Liu ,  Kung-Yen Su ,  Kai-Man Chan ,  Albert V. Kordesch

发明人： Chun-Mai Liu ,  Kung-Yen Su ,  Kai-Man Chan ,  Albert V. Kordesch

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A method for fabricating a triple self-aligned non-volatile memory device is disclosed. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.

摘要翻译： 公开了一种用于制造三重自对准非易失性存储器件的方法。 该方法包括在衬底上形成隔离氧化物。 通过将第一多晶硅层沉积并自对准到隔离氧化物来形成多个浮栅。 然后在浮动栅极之间的衬底上限定公共源极区域。 第二多晶硅层沉积在公共源区上并相对于隔离氧化物自对准。 第三多晶硅层沉积在多个浮动栅极附近。 然后通过将第三多晶硅层自对准到隔离氧化物来形成多个选择栅极。 此外，在衬底上限定至少一个漏极区域。

公开(公告)号：US06489200B1

公开(公告)日：2002-12-03

申请号：US09613495

申请日：2000-07-11

申请人： Len-Yi Leu ,  Chun-Mai Liu ,  Ken Su ,  Albert V. Kordesch

发明人： Len-Yi Leu ,  Chun-Mai Liu ,  Ken Su ,  Albert V. Kordesch

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/3144 ,  H01L27/0629 ,  H01L27/115 ,  H01L28/40

摘要： A method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.

摘要翻译： 在衬底上形成电容器的方法包括形成覆盖衬底的第一多晶硅层以限定浮动栅极。 形成覆盖第一多晶硅层的第二多晶硅以限定电容器的控制栅极和第一电极。 在第二多晶硅层上形成电介质层。 在电介质层上形成第三多晶硅层。 蚀刻第三多晶硅层以限定电容器的第二电极。 此后，蚀刻介电层。