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公开(公告)号：US09946022B2
公开(公告)日：2018-04-17
申请号：US15365548
申请日：2016-11-30
Applicant: Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
Inventor： Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
CPC classification number: G02B6/136 , G02B6/12004 , G02B6/122 , G02B6/1225 , G02B6/132 , G02B6/305 , G02B2006/12061 , G02B2006/12097 , G02B2006/121 , G02B2006/12107 , G02B2006/12123 , G02F1/0147 , G02F1/025 , G02F2001/0151
Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.
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公开(公告)号：US20170146740A1
公开(公告)日：2017-05-25
申请号：US15365548
申请日：2016-11-30
Applicant: Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
Inventor： Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
CPC classification number: G02B6/136 , G02B6/12004 , G02B6/122 , G02B6/1225 , G02B6/132 , G02B6/305 , G02B2006/12061 , G02B2006/12097 , G02B2006/121 , G02B2006/12107 , G02B2006/12123 , G02F1/0147 , G02F1/025 , G02F2001/0151
Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.
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公开(公告)号：US09529150B2
公开(公告)日：2016-12-27
申请号：US14520893
申请日：2014-10-22
Applicant: Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
Inventor： Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
CPC classification number: G02B6/136 , G02B6/12004 , G02B6/122 , G02B6/1225 , G02B6/132 , G02B6/305 , G02B2006/12061 , G02B2006/12097 , G02B2006/121 , G02B2006/12107 , G02B2006/12123 , G02F1/0147 , G02F1/025 , G02F2001/0151
Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.
Abstract translation: 在标准电子工艺中集成波导的常规方法通常涉及在铸造工艺中使用介电层，例如多晶硅，单晶硅或氮化硅，或者在后端中沉积和图案化电介质层作为后铸造 处理。 在本方法中，在铸造处理之后，硅手柄的后端被蚀刻掉以暴露使用标准铸造处理（例如，互补金属氧化物半导体（CMOS）处理）限定的空隙或沟槽。 将介电材料沉积到空隙或沟槽中产生集成在晶片前端内的光波导。 例如，形成在铸造中的浅沟槽隔离（STI）层可以在模具或晶片的前端内的镶嵌工艺中用作高分辨率图案化波导模板。 使用高折射率介电材料填充沟槽产生可以引导可见光和/或红外光的波导，这取决于波导的尺寸和折射率对比度。
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公开(公告)号：US20150125111A1
公开(公告)日：2015-05-07
申请号：US14520893
申请日：2014-10-22
Applicant: Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
Inventor： Jason Scott Orcutt , Karan Kartik Mehta , Rajeev Jagga Ram , Amir Hossein Atabaki
CPC classification number: G02B6/136 , G02B6/12004 , G02B6/122 , G02B6/1225 , G02B6/132 , G02B6/305 , G02B2006/12061 , G02B2006/12097 , G02B2006/121 , G02B2006/12107 , G02B2006/12123 , G02F1/0147 , G02F1/025 , G02F2001/0151
Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.
Abstract translation: 在标准电子工艺中集成波导的常规方法通常涉及在铸造工艺中使用介电层，例如多晶硅，单晶硅或氮化硅，或者在后端中沉积和图案化电介质层作为后铸造 处理。 在本方法中，在铸造处理之后，硅手柄的后端被蚀刻掉以暴露使用标准铸造处理（例如，互补金属氧化物半导体（CMOS）处理）限定的空隙或沟槽。 将介电材料沉积到空隙或沟槽中产生集成在晶片前端内的光波导。 例如，形成在铸造中的浅沟槽隔离（STI）层可以在模具或晶片的前端内的镶嵌工艺中用作高分辨率图案化波导模板。 使用高折射率介电材料填充沟槽产生可以引导可见光和/或红外光的波导，这取决于波导的尺寸和折射率对比度。
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