公开(公告)号：US20240012213A1

公开(公告)日：2024-01-11

申请号：US18471323

申请日：2023-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yuan Yu ,  Hung-Yi Kuo ,  Cheng-Chieh Hsieh ,  Hao-Yi Tsai ,  Chung-Ming Weng ,  Hua-Kuei Lin ,  Che-Hsiang Hsu

IPC: G02B6/42 ,  H01L25/16 ,  G02B6/12

CPC classification number: G02B6/4251 ,  H01L25/167 ,  G02B6/12004 ,  G02B6/12002 ,  G02B6/12 ,  G02B2006/12061 ,  G02B2006/121 ,  H01L23/562

Abstract: A photonic integrated circuit has a central region and a peripheral region surrounding the central region. The photonic integrated circuit includes a semiconductor layer, a seal ring structure, and a plurality of silicon waveguides. The seal ring structure is disposed on the semiconductor layer. The seal ring structure is located in the peripheral region and has at least one recess recessing towards the central region from a top view. The seal ring structure is a continuous structure from the top view. The silicon waveguides are embedded in the semiconductor layer.

公开(公告)号：US20190244866A1

公开(公告)日：2019-08-08

申请号：US16317171

申请日：2017-07-13

Applicant: ROCKLEY PHOTONICS LIMITED

Inventor： Aaron ZILKIE ,  Andrew RICKMAN ,  Damiana LEROSE

IPC: H01L21/8238 ,  G02B6/13 ,  G02B6/136 ,  H01L21/8258

CPC classification number: G02B6/305 ,  G02B6/12 ,  G02B6/12004 ,  G02B6/1223 ,  G02B6/131 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/121 ,  G02B2006/12147 ,  G02B2006/12152 ,  G02B2006/12176 ,  G02B2006/12178 ,  G02B2006/12195 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/823821 ,  H01L21/8258 ,  H01S5/021 ,  H01S5/0216

Abstract: A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 μm to 13 μm.

公开(公告)号：US10054745B2

公开(公告)日：2018-08-21

申请号：US15461789

申请日：2017-03-17

Applicant: Cisco Technology, Inc.

Inventor： Mark Webster ,  Ravi Sekhar Tummidi

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/122

CPC classification number: G02B6/30 ,  G02B6/107 ,  G02B6/12 ,  G02B6/12002 ,  G02B6/122 ,  G02B6/1228 ,  G02B6/132 ,  G02B6/14 ,  G02B6/305 ,  G02B6/43 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/121 ,  G02B2006/12147 ,  G02B2006/12152

Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.

公开(公告)号：US09971096B2

公开(公告)日：2018-05-15

申请号：US15169836

申请日：2016-06-01

Applicant: Cisco Technology, Inc.

Inventor： Kal Shastri ,  Rao Yelamarty ,  Neeraj Dubey ,  David Piede ,  Weizhuo Li

IPC: G02B6/30 ,  G02B6/36 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02B6/30 ,  G02B6/136 ,  G02B6/3652 ,  G02B6/3692 ,  G02B2006/12097 ,  G02B2006/121

Abstract: Embodiments herein include an optical system that passively aligns a fiber array connector (FAC) to a waveguide in a photonic chip. A substrate of the FAC is machined or etched to include multiple grooves along a common axis or plane to hold optical waveguides, or more specifically, the fibers of the optical cables in the FAC. To align the fibers to the photonic chip, one of the fibers is disposed in an alignment trench which has a width that is substantially the same as the diameter of the fiber. When the fiber registers with the alignment trench, the fiber is aligned with a waveguide disposed at the end of the trench. Because the pitch between the fibers can be precisely controlled, aligning one of the fibers using the alignment trench results in the other fibers becoming passively aligned to respective waveguides in the photonic chip.

公开(公告)号：US09946022B2

公开(公告)日：2018-04-17

申请号：US15365548

申请日：2016-11-30

Applicant: Jason Scott Orcutt ,  Karan Kartik Mehta ,  Rajeev Jagga Ram ,  Amir Hossein Atabaki

Inventor： Jason Scott Orcutt ,  Karan Kartik Mehta ,  Rajeev Jagga Ram ,  Amir Hossein Atabaki

IPC: G02B6/136 ,  G02B6/132 ,  G02F1/025 ,  G02B6/122 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/305 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12123 ,  G02F1/0147 ,  G02F1/025 ,  G02F2001/0151

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.

公开(公告)号：US09874689B2

公开(公告)日：2018-01-23

申请号：US15111418

申请日：2015-01-14

Applicant: Massachusetts Institute Of Technology (MIT) ,  National University of Singapore ,  Nanyang Technological University

Inventor： Wenjia Zhang ,  Bing Wang ,  Li Zhang ,  Zhaomin Zhu ,  Jurgen Michel ,  Soo-Jin Chua ,  Li-Shiuan Peh ,  Siau Ben Chiah ,  Eng Kian Kenneth Lee

IPC: G02B6/42 ,  G02B6/12 ,  H01L27/15 ,  H01L31/12 ,  H01L21/8258 ,  H01L27/06 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/0392 ,  H01L31/153 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L33/00

CPC classification number: G02B6/12004 ,  G02B6/00 ,  G02B6/12 ,  G02B6/428 ,  G02B2006/121 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/15 ,  H01L31/02327 ,  H01L31/03044 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/035281 ,  H01L31/0392 ,  H01L31/105 ,  H01L31/12 ,  H01L31/125 ,  H01L31/153 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32

Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

公开(公告)号：US09831374B2

公开(公告)日：2017-11-28

申请号：US15038445

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Benjamin Vincent ,  Avi Feshali

IPC: H01L31/0232 ,  H01L31/105 ,  G02B6/122 ,  H01L31/028 ,  H01L31/18 ,  G02B6/42 ,  G02B6/12

CPC classification number: H01L31/105 ,  G02B6/1228 ,  G02B6/4295 ,  G02B2006/121 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1804 ,  Y02E10/52

Abstract: Techniques and mechanisms for providing efficient direction of light to a photodetector with a tapered waveguide structure. In an embodiment, a taper structure of a semiconductor device comprises a substantially single crystalline silicon. A buried oxide underlies and adjoins the monocrystalline silicon of the taper structure, and a polycrystalline Si is disposed under the buried oxide. During operation of the semiconductor device light is redirected in the taper structure and received via a first side of a Germanium photodetector. In another embodiment, one or more mirror structures positioned on a far side of the Germanium photodetector may provide for a portion of the light to be reflected back to the Germanium photodetector.

公开(公告)号：US09817197B2

公开(公告)日：2017-11-14

申请号：US15087278

申请日：2016-03-31

Applicant: Coriant Advanced Technology, LLC

Inventor： David Henry Kinghorn ,  Ari Jason Novack ,  Holger N. Klein ,  Nathan A. Nuttall ,  Kishor V. Desai ,  Daniel J. Blumenthal ,  Michael J. Hochberg ,  Ruizhi Shi

IPC: G02B6/42 ,  G02B6/13 ,  G02B6/136 ,  H01L31/12 ,  H01L31/18 ,  H01L25/00 ,  G02B6/12 ,  H01L25/16

CPC classification number: G02B6/423 ,  G02B6/131 ,  G02B6/136 ,  G02B6/4238 ,  G02B6/4251 ,  G02B6/4268 ,  G02B6/4274 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/121 ,  H01L25/16 ,  H01L25/162 ,  H01L25/167 ,  H01L25/50 ,  H01L31/125 ,  H01L31/18 ,  Y02P70/521

Abstract: Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.

公开(公告)号：US09746607B2

公开(公告)日：2017-08-29

申请号：US15147611

申请日：2016-05-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tom Collins ,  Marco Lamponi

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125

CPC classification number: G02B6/1228 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/125 ,  G02B2006/121 ,  G02B2006/12147

Abstract: The present invention provides a waveguide structure for optical coupling. The waveguide structure includes a first waveguide embedded in a cladding of lower refractive index than the first waveguide, and a second waveguide of higher refractive index than the cladding and distanced from the first waveguide. The waveguide structure further includes an intermediate waveguide, of which at least a part is arranged between the first waveguide and the second waveguide. The first waveguide and the second waveguide each comprise a tapered end for coupling light into and/or out of the intermediate waveguide.

公开(公告)号：US09709734B2

公开(公告)日：2017-07-18

申请号：US15085766

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Mahesh Krishnamurthi ,  Judson Ryckman ,  Haisheng Rong ,  Ling Liao ,  Harel Frish ,  Oshrit Harel ,  Assia Barkai ,  Yun-Chung Na ,  Han-Din Liu

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/42 ,  G02B6/132 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/4296 ,  G02B2006/12061 ,  G02B2006/121 ,  G02B2006/12104 ,  G02B2006/12147 ,  G02B2006/12152

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for an optical coupler. In some embodiments, the device may include an optical waveguide to transmit light input from a light source. The optical waveguide may include a semiconductor layer, having a trench with one facet that comprises an edge formed under an approximately 45 degree angle and another facet formed substantially normal to the semiconductor layer. The edge may interface with another medium to form a mirror to receive inputted light and reflect received light substantially perpendicularly to propagate the received light. Other embodiments may be described and/or claimed.