公开(公告)号：US06399497B2

公开(公告)日：2002-06-04

申请号：US09739228

申请日：2000-12-19

申请人： Katsuhisa Sakai

发明人： Katsuhisa Sakai

IPC分类号： H01L21302

CPC分类号： H01L21/32136 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/76838

摘要： A tungsten film 20 is formed over a titanium-base film 18 to provide an interconnecting layer 22. An anti-reflection film 26 is formed over the interconnecting layer 22. Further, a photoresist 28 is applied over the anti-reflection film 26, followed by patterning. Using a mixed gas of SF6 and Cl2, the anti-reflection film 26 is etched. With a mixed gas of SF6 and Cl2, the tungsten film 20 is then etched. After that, the titanium-base film 18 is etched using a mixed gas of Cl2 and BCl3.

摘要翻译： 在钛基膜18上形成钨膜20以提供互连层22.在互连层22上形成防反射膜26.此外，将光致抗蚀剂28施加在抗反射膜26上，随后 通过图案化。 使用SF6和Cl2的混合气体，蚀刻抗反射膜26。 用SF6和Cl2的混合气体，然后蚀刻钨膜20。 之后，使用Cl 2和BCl 3的混合气体蚀刻钛基膜18。

公开(公告)号：US4841017A

公开(公告)日：1989-06-20

申请号：US167680

申请日：1988-03-11

申请人： Takaaki Murai ,  Katsuhisa Sakai

发明人： Takaaki Murai ,  Katsuhisa Sakai

IPC分类号： C08G59/02 ,  C08G59/34 ,  C08G65/14

CPC分类号： C08G59/027 ,  C08G59/02 ,  C08G65/14

摘要： Disclosed as a polyether compound having ether groups and vinyl double bonds represented by formula (I) ##STR1## and an epoxy resin represented by formula (II) ##STR2## wherein R.sup.1 represents a residue group of an organic compound having l active hydrogen atoms, n1 through nl each represents 0 or an integer of from 1 to 100, the sum of integers represented by n1 through nl is from 1 to 100, and l represents an integer of from 1 to 100, and A represents from 1 to 100, and A represents ##STR3## or a mixture of ##STR4## wherein R.sup.2 represents a residue group of mono epoxy compound, and B represents ##STR5## or a mixture of ##STR6## wherein X represents a ##STR7## group, wherein R.sup.3 represents a hydrogen atom, an alkyl group, an alkyl carbonyl group, or an arylcarbonyl group, provided that the epoxy resin represented by formula (II) contains at least one ##STR8## group: In a further aspect, the invention relates to processes for production thereof.

公开(公告)号：US07301237B2

公开(公告)日：2007-11-27

申请号：US11229550

申请日：2005-09-20

申请人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

发明人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/76829 ,  H01L21/76834

摘要： An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.

摘要翻译： 在层间绝缘膜上形成蚀刻停止膜。 在蚀刻停止膜上形成导电层。 形成蚀刻停止膜以覆盖导电层。 在蚀刻停止膜上形成层间绝缘膜。 在上述结构中，首先在第一蚀刻条件下形成垂直贯穿层间绝缘膜的用于暴露蚀刻阻挡膜的表面的孔。 此后，在第二蚀刻条件下去除用作孔底的蚀刻阻挡膜，从而形成到达导电层的孔。 孔中嵌有互连。 由此，能够防止到达导电层的空穴的延伸到作为未对准的下层间绝缘膜的半导体装置及其制造方法。

公开(公告)号：US06769960B2

公开(公告)日：2004-08-03

申请号：US10309119

申请日：2002-12-04

申请人： Katsuhisa Sakai

发明人： Katsuhisa Sakai

IPC分类号： B24B100

CPC分类号： B24B37/04 ,  B24B49/10 ,  B24B57/02

摘要： An apparatus for manufacturing a semiconductor device by polishing the surface of a semiconductor substrate is provided, which comprises a polishing pad for polishing the substrate surface, a polishing slurry feed apparatus for feeding a polishing slurry to the substrate surface, and a measuring instrument including an electrode (A) and an electrode (B) immersed in a polishing slurry, wherein a characteristic variation of the polishing slurry is detected from a variation in value of an electric current passing between the electrode (A) and the electrode (B) or from a variation in potential difference between the electrodes.

摘要翻译： 提供一种通过研磨半导体衬底的表面来制造半导体器件的装置，其包括用于抛光衬底表面的抛光垫，用于将抛光浆料供给到衬底表面的抛光浆料进料装置，以及包括 电极（A）和浸渍在研磨浆料中的电极（B），其中根据通过电极（A）和电极（B）的电流值的变化或从电极（A）和电极 电极之间的电位差的变化。

公开(公告)号：US5122586A

公开(公告)日：1992-06-16

申请号：US318309

申请日：1989-03-03

申请人： Katsuhisa Sakai ,  Hiroyuki Oshima

发明人： Katsuhisa Sakai ,  Hiroyuki Oshima

IPC分类号： C08G59/34

CPC分类号： C08G59/027

摘要： Disclosed are a composition comprising polyether compounds, obtained by addition copolymerization of a mixture of 4-vinylcyclohexene-1-oxide and a compound having at least two epoxy groups with a compound having at least one active hydrogen atom, and a composition comprising epoxy compounds obtained by epoxidation of the composition of the polyether compounds. The invention also relates to processes for production thereof.The disclosed composition comprising epoxy compounds has a higher softening temperature compared that produced by polymerization of only 4-vinylcyclohexene-1-oxide with a compound having at least one active hydrogen atom.

公开(公告)号：US07465662B2

公开(公告)日：2008-12-16

申请号：US11907438

申请日：2007-10-12

申请人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

发明人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

IPC分类号： H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/76829 ,  H01L21/76834

摘要： A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive layer is formed on the first etching stopper film. A second etching stopper film is formed to cover the conductive layer, an upper surface of the conductive layer and both side surfaces of the conductive layer. A second interlayer insulating film is formed on the second etching stopper film. A hole is formed penetrating the second interlayer insulating film in a direction of thickness and reaching the conductive layer. An interconnect is formed in the hole. The step of forming a hole includes etching the second interlayer insulating film under a first etching condition, and etching the second etching stopper film under a second etching condition different from the first etching condition.

摘要翻译： 通过包括形成第一层间绝缘膜的方法制造半导体器件。 第一蚀刻停止膜形成在第一层间绝缘膜上。 在第一蚀刻停止膜上形成导电层。 形成第二蚀刻阻挡膜以覆盖导电层，导电层的上表面和导电层的两个侧表面。 在第二蚀刻停止膜上形成第二层间绝缘膜。 在厚度方向上穿过第二层间绝缘膜并到达导电层的孔。 在孔中形成互连。 形成孔的步骤包括在第一蚀刻条件下蚀刻第二层间绝缘膜，并且在与第一蚀刻条件不同的第二蚀刻条件下蚀刻第二蚀刻阻挡膜。

公开(公告)号：US20080045006A1

公开(公告)日：2008-02-21

申请号：US11907438

申请日：2007-10-12

申请人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

发明人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76829 ,  H01L21/76834

摘要： An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.

摘要翻译： 在层间绝缘膜上形成蚀刻停止膜。 在蚀刻停止膜上形成导电层。 形成蚀刻停止膜以覆盖导电层。 在蚀刻停止膜上形成层间绝缘膜。 在上述结构中，首先在第一蚀刻条件下形成垂直贯穿层间绝缘膜的用于暴露蚀刻阻挡膜的表面的孔。 此后，在第二蚀刻条件下去除用作孔底的蚀刻阻挡膜，从而形成到达导电层的孔。 孔中嵌有互连。 由此，能够防止到达导电层的空穴的延伸到作为未对准的下层间绝缘膜的半导体装置及其制造方法。

公开(公告)号：US20060063372A1

公开(公告)日：2006-03-23

申请号：US11229550

申请日：2005-09-20

申请人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

发明人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76829 ,  H01L21/76834

摘要： An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.

摘要翻译： 在层间绝缘膜上形成蚀刻停止膜。 在蚀刻停止膜上形成导电层。 形成蚀刻停止膜以覆盖导电层。 在蚀刻停止膜上形成层间绝缘膜。 在上述结构中，首先在第一蚀刻条件下形成垂直贯穿层间绝缘膜的用于暴露蚀刻阻挡膜的表面的孔。 此后，在第二蚀刻条件下去除用作孔底的蚀刻阻挡膜，从而形成到达导电层的孔。 孔中嵌有互连。 由此，能够防止到达导电层的空穴的延伸到作为未对准的下层间绝缘膜的半导体装置及其制造方法。

公开(公告)号：US06872656B2

公开(公告)日：2005-03-29

申请号：US10462699

申请日：2003-06-17

申请人： Katsuhisa Sakai

发明人： Katsuhisa Sakai

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76877

摘要： A semiconductor device includes a first interconnection, an interlayer insulation film covering the first interconnection a contact hole provided in the interlayer insulation film and reaching the first interconnection, a first barrier metal and a tungsten plug provided in the contact hole, an oxide film provided at a surface of the tungsten plug, and a second barrier metal and a second interconnection provided on the oxide film.

摘要翻译： 一种半导体器件，包括第一互连层，覆盖第一互连层的层间绝缘膜，设置在层间绝缘膜中并到达第一互连的接触孔，设置在接触孔中的第一阻挡金属和钨丝塞， 钨塞的表面，以及设置在氧化物膜上的第二阻挡金属和第二互连。

公开(公告)号：US20090137114A1

公开(公告)日：2009-05-28

申请号：US12273795

申请日：2008-11-19

申请人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

发明人： Katsuhiro Uesugi ,  Katsuo Katayama ,  Katsuhisa Sakai

IPC分类号： H01L21/441

CPC分类号： H01L21/76802 ,  H01L21/76829 ,  H01L21/76834

摘要： A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive layer is formed on the first etching stopper film. A second etching stopper film is formed to cover the conductive layer, an upper surface of the conductive layer and both side surfaces of the conductive layer. A second interlayer insulating film is formed on the second etching stopper film. A hole is formed penetrating the second interlayer insulating film in a direction of thickness and reaching the conductive layer. An interconnect is formed in the hole. The step of forming a hole includes etching the second interlayer insulating film under a first etching condition, and etching the second etching stopper film under a second etching condition different from the first etching condition. The second etching condition includes using an etching gas containing C, F, and H.

摘要翻译： 通过包括形成第一层间绝缘膜的方法制造半导体器件。 第一蚀刻停止膜形成在第一层间绝缘膜上。 在第一蚀刻停止膜上形成导电层。 形成第二蚀刻阻挡膜以覆盖导电层，导电层的上表面和导电层的两个侧表面。 在第二蚀刻停止膜上形成第二层间绝缘膜。 在厚度方向上穿过第二层间绝缘膜并到达导电层的孔。 在孔中形成互连。 形成孔的步骤包括在第一蚀刻条件下蚀刻第二层间绝缘膜，并且在与第一蚀刻条件不同的第二蚀刻条件下蚀刻第二蚀刻阻挡膜。 第二蚀刻条件包括使用含有C，F和H的蚀刻气体。