公开(公告)号：US06900691B2

公开(公告)日：2005-05-31

申请号：US10751522

申请日：2004-01-06

Applicant: Katsuya Furue

Inventor： Katsuya Furue

IPC: G01R31/28 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  H01L25/00

CPC classification number: G01R31/2884

Abstract: A semiconductor integrated circuit includes a first pad mounted on a main surface of a semiconductor substrate, a second pad mounted on the main surface and positioned adjacent to the first pad, a pad joint mounted between the first pad and the second pad to connect the first pad and the second pad, a first signal input/output circuit including a first output buffer connected to the first pad, a second signal input/output circuit including a second input buffer connected to the second pad, and a second output buffer connected to the second pad and including an output section having a controllable output impedance, an input/output signal control circuit connected to the first signal input/output circuit and the second signal input/output circuit. The input/output signal control circuit includes a first latch circuit connected to an input section of the first output buffer, a second latch circuit connected to an output section of the second input buffer, and a control switch connected to an input section of the first output buffer and an input section of the second output buffer.

公开(公告)号：US20050046473A1

公开(公告)日：2005-03-03

申请号：US10751522

申请日：2004-01-06

Applicant: Katsuya Furue

Inventor： Katsuya Furue

IPC: G01R31/28 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  H01L25/00

CPC classification number: G01R31/2884

Abstract: A semiconductor integrated circuit includes a first pad mounted on a main surface of a semiconductor substrate, a second pad mounted on the main surface and positioned adjacent to the first pad, a pad joint mounted between the first pad and the second pad to connect the first pad and the second pad, a first signal input/output circuit including a first output buffer connected to the first pad, a second signal input/output circuit including a second input buffer connected to the second pad, and a second output buffer connected to the second pad and including an output section having a controllable output impedance, an input/output signal control circuit connected to the first signal input/output circuit and the second signal input/output circuit. The input/output signal control circuit includes a first latch circuit connected to an input section of the first output buffer, a second latch circuit connected to an output section of the second input buffer, and a control switch connected to an input section of the first output buffer and an input section of the second output buffer.

Abstract translation: 半导体集成电路包括安装在半导体基板的主表面上的第一焊盘，安装在主表面上并邻近第一焊盘定位的第二焊盘，安装在第一焊盘和第二焊盘之间的焊盘接头，用于连接第一焊盘 焊盘和第二焊盘，包括连接到第一焊盘的第一输出缓冲器的第一信号输入/输出电路，包括连接到第二焊盘的第二输入缓冲器的第二信号输入/输出电路和连接到第二焊盘的第二输出缓冲器 第二焊盘并且包括具有可控输出阻抗的输出部分，连接到第一信号输入/输出电路和第二信号输入/输出电路的输入/输出信号控制电路。 输入/输出信号控制电路包括连接到第一输出缓冲器的输入部分的第一锁存电路，连接到第二输入缓冲器的输出部分的第二锁存电路和连接到第一输出缓冲器的输入部分的控制开关 输出缓冲器和第二输出缓冲器的输入部分。

公开(公告)号：US06646461B2

公开(公告)日：2003-11-11

申请号：US09840069

申请日：2001-04-24

Applicant: Kazushi Sugiura ,  Katsuya Furue

Inventor： Kazushi Sugiura ,  Katsuya Furue

IPC: G01R3126

CPC classification number: G01R31/3193 ,  G01R31/318505 ,  G01R31/3187

Abstract: A semiconductor device testing method is disclosed which comprises a first process 39, a second process 41 and a third process 43. In the first process 39, a test function part of a semiconductor device having a built-in self-test function is subjected to a self-diagnostic test, and a main circuit part of the device in question is tested by its test function part. If the result of either of the two tests on the device turns out to be abnormal, the device in question is rejected as defective. The test results are saved. In the second process 41, the main circuit part of each semiconductor device rejected as defective in the first process 39 is tested by use of an external test signal. If the result of the test on the semiconductor device judged faulty in the first process 39 turns out to be normal in the second process 41, then the device in question is judged normal in the third process 43.

Abstract translation: 公开了一种半导体器件测试方法，其包括第一处理39，第二处理41和第三处理43.在第一处理39中，将具有内置自检功能的半导体器件的测试功能部分 通过其测试功能部件测试所述设备的自诊断测试和主电路部分。 如果设备中的两个测试中的任一个的结果证明是异常的，则所讨论的设备被拒绝为有缺陷的。 测试结果被保存。 在第二处理41中，通过使用外部测试信号来测试在第一处理39中被拒绝为缺陷的每个半导体器件的主电路部分。 如果在第一处理39中判定为错误的半导体器件的测试结果在第二处理41中变得正常，则在第三处理43中判断正确的设备。

公开(公告)号：US06962827B1

公开(公告)日：2005-11-08

申请号：US10640322

申请日：2003-08-14

Applicant: Katsuya Furue ,  Shigeru Kikuda ,  Kiyohiro Furutani ,  Tetsushi Tanizaki ,  Shigehiro Kuge ,  Takashi Kono

Inventor： Katsuya Furue ,  Shigeru Kikuda ,  Kiyohiro Furutani ,  Tetsushi Tanizaki ,  Shigehiro Kuge ,  Takashi Kono

IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/12 ,  G11C29/56 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L22/34 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/0403 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.

Abstract translation: 多个半导体集成电路和多个TEG电路对准并设置在基板上。 在TEG电路中，在穿过切割线区域的面向半导体集成电路的区域中提供内置测试电路。 内置测试电路和半导体集成电路通过设置在切割线区域上的互连来连接。 互连被切割以分离成芯片。