公开(公告)号：US6073249A

公开(公告)日：2000-06-06

申请号：US140797

申请日：1998-08-26

申请人： Toru Watabe ,  Yasutomo Sakurai ,  Takumi Kishino ,  Yoshio Hirose ,  Koichi Odahara ,  Kazuhiro Nonomura ,  Takumi Takeno ,  Shinya Katoh ,  Takato Noda

发明人： Toru Watabe ,  Yasutomo Sakurai ,  Takumi Kishino ,  Yoshio Hirose ,  Koichi Odahara ,  Kazuhiro Nonomura ,  Takumi Takeno ,  Shinya Katoh ,  Takato Noda

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F13/00

CPC分类号： G06F11/1658 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/182 ,  G06F11/2041 ,  G06F11/1402 ,  G06F11/1675 ,  G06F11/22

摘要： A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

摘要翻译： TMR单元通过总线连接多个处理器，并且同时执行相同的处理操作。 在多个处理器中，其中之一是主机，其余的处理器是从机。 仅由主处理器形成的信息被输出到总线。 每个处理器具有多路复用控制电路。 多路复用控制电路将自身形成的输出信息与输出到总线的总线信息进行比较，从而检测故障并允许内部电路执行必要的处理。

公开(公告)号：US5835697A

公开(公告)日：1998-11-10

申请号：US674786

申请日：1996-07-03

申请人： Toru Watabe ,  Yasutomo Sakurai ,  Takumi Kishino ,  Yoshio Hirose ,  Koichi Odahara ,  Kazuhiro Nonomura ,  Takumi Takeno ,  Shinya Katoh ,  Takato Noda

发明人： Toru Watabe ,  Yasutomo Sakurai ,  Takumi Kishino ,  Yoshio Hirose ,  Koichi Odahara ,  Kazuhiro Nonomura ,  Takumi Takeno ,  Shinya Katoh ,  Takato Noda

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F13/00

CPC分类号： G06F11/1658 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/182 ,  G06F11/2041 ,  G06F11/1402 ,  G06F11/1675 ,  G06F11/22

摘要： A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.