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    Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units
    3.
    发明授权
    Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units 失效
    信息处理系统，其中响应于从多个处理单元发出的访问请求来访问存储器件和标签副本

    公开(公告)号：US06292870B1

    公开(公告)日：2001-09-18

    申请号：US09020678

    申请日：1998-02-09

    申请人： Takaharu Ishizuka ,  Takato Noda ,  Yasuhide Shibata ,  Takumi Takeno ,  Katsunori Takeshita ,  Fumitake Sugano

    发明人： Takaharu Ishizuka ,  Takato Noda ,  Yasuhide Shibata ,  Takumi Takeno ,  Katsunori Takeshita ,  Fumitake Sugano

    IPC分类号： G06F1208

    CPC分类号： G06F12/0822

    摘要： Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.

    摘要翻译： 每个具有第一存储器和系统控制器的处理单元通过总线互连。 系统控制器包括访问控制单元，用于控制对处理单元中的第一存储器的标签的拷贝的访问以及访问多个通路所引导的第二存储器，从而控制对由处理单元请求的存储器或存储器访问的访问。 在信息处理系统中，包括多个存储器接口，用于在交织的基础上访问第二存储器。 此外，包括与存储器接口的数量相同数量的标签和存储器访问控制单元的副本，以使得能够在交织的基础上访问标签。 由于因此能够进行基于交织的存储器和标签的访问，即使处理单元的数量增加，对存储器访问控制单元的竞争减少，并且存储器访问的效率提高。

    Processor having cache purge controller
    4.
    发明授权
    Processor having cache purge controller 失效
    处理器具有缓存清除控制器

    公开(公告)号：US06697917B1

    公开(公告)日：2004-02-24

    申请号：US09537356

    申请日：2000-03-29

    申请人： Junya Matsushima ,  Takumi Takeno ,  Kenichi Nabeya ,  Daisuke Ban

    发明人： Junya Matsushima ,  Takumi Takeno ,  Kenichi Nabeya ,  Daisuke Ban

    IPC分类号： G06F1200

    CPC分类号： G06F12/0891

    摘要： The present invention prevents, at high speed, a malfunction from occurring at the time of changing a mode in a processor, in which information to be decoded varies with modes. The processor is provided with a circuit for referring to a result of decoding information or issuing an instruction when a write operation is performed on a register for storing data containing a bit that indicates a current mode, and for outputting a purge signal if the result of decoding information or issuing an instruction is information represented by a mode switching signal. Thus, when a mode switching signal is written to the register, a purge signal is outputted to a cache memory. Consequently, the valid bit of prefetched cache data is turned off. This prevents prefetched data from being decoded in a different mode. As a result, operations are normally performed after the switching of the mode. Alternatively, the purge signal is outputted by detecting a change in the value of the bit indicating the current mode.

    摘要翻译： 本发明能够高速地防止在改变要解码的信息随模式变化的处理器中的模式发生时发生故障。 处理器设置有用于在对用于存储指示当前模式的位的数据的存储器的寄存器执行写入操作时参考解码信息的结果或发出指令的电路，并且如果结果为 解码信息或发出指令是由模式切换信号表示的信息。 因此，当模式切换信号被写入寄存器时，清除信号被输出到高速缓冲存储器。 因此，预取高速缓存数据的有效位被关闭。 这防止了以不同模式解码预取数据。 结果，通常在切换模式之后执行操作。 或者，通过检测表示当前模式的位的值的变化来输出清除信号。

    Processor
    5.
    发明授权
    Processor 失效
    处理器

    公开(公告)号：US06647488B1

    公开(公告)日：2003-11-11

    申请号：US09614455

    申请日：2000-07-12

    申请人： Takumi Takeno ,  Kenichi Nabeya ,  Junya Matsushima ,  Daisuke Ban

    发明人： Takumi Takeno ,  Kenichi Nabeya ,  Junya Matsushima ,  Daisuke Ban

    IPC分类号： G06F930

    CPC分类号： G06F9/3822 ,  G06F9/3017 ,  G06F9/3802

    摘要： A processor is adapted to support a complex instruction set without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions in hardware. The processor is implemented by adding, to the existing processor, a second instruction decoder for decoding an expanded instruction code not capable of issuing an instruction per cycle, and for issuing one instruction per cycle by translating the expanded instruction code into a sequence of basic instructions; a counter for counting the number of instructions to be issued by the second instruction decoder, and for outputting a signal indicating that the expanded instruction code is being executed; and an instruction selection unit for selecting the instruction issued from the first instruction decoder when executing a basic instruction code and the instruction issued from the second instruction decoder when executing the expanded instruction code.

    摘要翻译： 处理器适于支持复杂指令集而不对现有硬件进行重大修改，而是仅添加几个控制，从而在硬件中仿真指令。 处理器通过向现有处理器添加第二指令解码器来实现，该第二指令解码器用于对不能每周期发出指令的扩展指令代码进行解码，并且通过将扩展指令代码转换成基本指令序列来发出每个周期一个指令 ; 计数器，用于对由第二指令解码器发出的指令数进行计数，并输出指示扩展指令代码正在执行的信号; 以及指令选择单元，用于在执行基本指令代码时执行从第一指令解码器发出的指令以及当执行扩展指令代码时从第二指令解码器发出的指令。