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    Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units
    3.
    发明授权
    Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units 失效
    信息处理系统，其中响应于从多个处理单元发出的访问请求来访问存储器件和标签副本

    公开(公告)号：US06292870B1

    公开(公告)日：2001-09-18

    申请号：US09020678

    申请日：1998-02-09

    申请人： Takaharu Ishizuka ,  Takato Noda ,  Yasuhide Shibata ,  Takumi Takeno ,  Katsunori Takeshita ,  Fumitake Sugano

    发明人： Takaharu Ishizuka ,  Takato Noda ,  Yasuhide Shibata ,  Takumi Takeno ,  Katsunori Takeshita ,  Fumitake Sugano

    IPC分类号： G06F1208

    CPC分类号： G06F12/0822

    摘要： Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.

    摘要翻译： 每个具有第一存储器和系统控制器的处理单元通过总线互连。 系统控制器包括访问控制单元，用于控制对处理单元中的第一存储器的标签的拷贝的访问以及访问多个通路所引导的第二存储器，从而控制对由处理单元请求的存储器或存储器访问的访问。 在信息处理系统中，包括多个存储器接口，用于在交织的基础上访问第二存储器。 此外，包括与存储器接口的数量相同数量的标签和存储器访问控制单元的副本，以使得能够在交织的基础上访问标签。 由于因此能够进行基于交织的存储器和标签的访问，即使处理单元的数量增加，对存储器访问控制单元的竞争减少，并且存储器访问的效率提高。

    Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method
    4.
    发明授权
    Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method 失效
    具有高速缓存的信息处理装置中的缓存标签控制方法，具有高速缓存标签中的错误检查机制，以及使用该控制方法的信息处理装置

    公开(公告)号：US06681299B1

    公开(公告)日：2004-01-20

    申请号：US09537353

    申请日：2000-03-29

    申请人： Takayuki Shimamura ,  Shinya Kato ,  Takato Noda ,  Takumi Nonaka

    发明人： Takayuki Shimamura ,  Shinya Kato ,  Takato Noda ,  Takumi Nonaka

    IPC分类号： G06F906

    CPC分类号： G06F12/0802 ,  G06F11/1064

    摘要： To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a cache tag-RAM. At the time of retrieving the tags, both the true-tag and the shadow-tag are checked respectively to see whether there is an error in each tag. When an error has been detected, a hit decision is made by using a tag in which there is no error. Further, data within the cache tag-RAM is updated by using the tag in which there is no error, thereby correcting the error.

    摘要翻译： 提供能够纠正错误并且能够同时保持系统的高速操作的缓存标签控制方法。 附加有奇偶校验码的真实标签和具有真标签的反相极性的阴影标签分别存储在高速缓存标签RAM内的单独的地址中。 在检索标签时，分别检查true-tag和shadow-tag，以查看每个标签中是否有错误。 当检测到错误时，通过使用没有错误的标签进行命中判定。 此外，通过使用其中没有错误的标签来更新高速缓存标签-RAM内的数据，从而校正错误。