Phase synchronization apparatus and digital coherent light receiver
    3.
    发明授权
    Phase synchronization apparatus and digital coherent light receiver 有权
    相位同步装置和数字相干光接收机

    公开(公告)号:US08553825B2

    公开(公告)日:2013-10-08

    申请号:US12708859

    申请日:2010-02-19

    IPC分类号: H04L7/00

    CPC分类号: H04B10/61

    摘要: A phase synchronization method uses a removal path for removing an error component contained in an input signal and a delay addition path for adding a delay corresponding to a processing time period taken to remove the error component in the removal path. The removal path includes an averaging section. The averaging section includes a shift register and an obtaining unit. The shift register stores as many data as the maximum number of data to be averaged and successively receives processing data from which the error component has been extracted in the removal path. The obtaining unit obtains, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register.

    摘要翻译: 相位同步方法使用去除包含在输入信号中的误差分量的去除路径和用于增加与去除去除路径中的误差分量所花费的处理时间相对应的延迟的延迟相加路径。 去除路径包括平均部分。 平均部分包括移位寄存器和获取单元。 移位寄存器存储与要平均的数据的最大数量一样多的数据,并且连续地接收在删除路径中从其中提取了错误分量的处理数据。 获取单元从输入到移位寄存器的连续处理数据中,从移位寄存器中的中心附近的位置到两端的位置获得与要平均化的数据数量相同的处理数据。

    PHASE SYNCHRONIZATION APPARATUS AND DIGITAL COHERENT LIGHT RECEIVER
    7.
    发明申请
    PHASE SYNCHRONIZATION APPARATUS AND DIGITAL COHERENT LIGHT RECEIVER 有权
    相位同步装置和数字相干光接收器

    公开(公告)号:US20100239269A1

    公开(公告)日:2010-09-23

    申请号:US12708859

    申请日:2010-02-19

    IPC分类号: H04L7/02 H04B10/06

    CPC分类号: H04B10/61

    摘要: A phase synchronization method uses a removal path for removing an error component contained in an input signal and a delay addition path for adding a delay corresponding to a processing time period taken to remove the error component in the removal path. The removal path includes an averaging section. The averaging section includes a shift register and an obtaining unit. The shift register stores as many data as the maximum number of data to be averaged and successively receives processing data from which the error component has been extracted in the removal path. The obtaining unit obtains, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register.

    摘要翻译: 相位同步方法使用去除包含在输入信号中的误差分量的去除路径和用于增加与去除去除路径中的误差分量所花费的处理时间相对应的延迟的延迟相加路径。 去除路径包括平均部分。 平均部分包括移位寄存器和获取单元。 移位寄存器存储与要平均的数据的最大数量一样多的数据,并且连续地接收在删除路径中从其中提取了错误分量的处理数据。 获取单元从输入到移位寄存器的连续处理数据中,从移位寄存器中的中心附近的位置到两端的位置获得与要平均化的数据数量相同的处理数据。

    Multiplexing method and apparatus suitable for transmission of overhead data arriving from many communication lines
    8.
    发明授权
    Multiplexing method and apparatus suitable for transmission of overhead data arriving from many communication lines 有权
    适用于从许多通信线路到达的开销数据的传输的多路复用方法和装置

    公开(公告)号:US07106761B2

    公开(公告)日:2006-09-12

    申请号:US10075853

    申请日:2002-02-13

    IPC分类号: H04J3/02

    摘要: Data arriving from a plurality of channels asynchronously to each other are respectively stored in separate FIFOs (10). A controller (12) monitors the status of the FIFOs (10), retrieves the stored data in a predetermined order, and multiplexes the data, together with timing data indicating the presence or absence of the data, into a serial signal having a frame structure in which time slots are fixedly assigned to the respective channels. On the serial data, the same value appears successively as data, and when the data is valid, the corresponding timing data changes from a 0 to a 1. When the data is invalid, the value of the corresponding timing data does not change.

    摘要翻译: 从多个通道彼此异步到达的数据分别存储在单独的FIFO(10)中。 控制器(12)监视FIFO(10)的状态,以预定顺序检索存储的数据,并将数据与表示数据存在或不存在的定时数据一起复用到具有帧结构的串行信号 其中时隙被固定地分配给相应的信道。 在串行数据上,相同的值作为数据连续出现,当数据有效时,相应的定时数据从0变为1.当数据无效时,对应的定时数据的值不变。