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公开(公告)号：US20080233751A1
公开(公告)日：2008-09-25
申请号：US11690432
申请日：2007-03-23
IPC分类号： H01L21/461
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译： 公开了均匀地延迟IC芯片的方法。 一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。
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公开(公告)号：US07079381B2
公开(公告)日：2006-07-18
申请号：US10752969
申请日：2004-01-07
IPC分类号： G06F1/16
CPC分类号： H05K7/1454
摘要： An aligning apparatus comprising: a back plane, the back plane comprising at least one back plane connector; at least one daughter card, the daughter card comprising: a lower edge, the lower edge comprising a scalloped surface proximal to a rear surface of the lower edge, and a ramped surface proximal to a front surface of the lower edge; and a daughter card connector, the daughter card connector configured to be removably connectable to the back plane connector; and at least two guide rails extending from the back plane, the guide rail comprising a rear ramp and a front ramp. A method of aligning a daughter card to a back plane, the method comprising: sliding the daughter card towards the back plane; lifting the front end of the daughter; lifting the back end of the daughter card after lifting the front end of the daughter card; and providing the back end of the daughter card with a degree of freedom to lift and lower in order to align to the back plane, after lifting the back end of the daughter card.
摘要翻译： 一种对准装置，包括：背面，所述背面包括至少一个背面连接器; 至少一个子卡，所述子卡包括：下边缘，所述下边缘包括靠近所述下边缘的后表面的扇形表面，以及靠近所述下边缘的前表面的倾斜表面; 和子卡连接器，子卡连接器被配置为可拆卸地连接到背板连接器; 以及从后平面延伸的至少两个导轨，所述导轨包括后斜面和前斜面。 一种将子卡对准背板的方法，所述方法包括：将子卡朝着背面平面滑动; 抬起女儿的前端; 抬起子卡前端提起子卡的后端; 并且在提起子卡的后端之后，提供子卡的后端具有提升和降低的自由度以便与背板对准。
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3.发明授权Method of TEM sample preparation for electron holography for semiconductor devices 失效半导体器件电子全息术的TEM样品制备方法公开(公告)号：US07560692B2
公开(公告)日：2009-07-14
申请号：US11617386
申请日：2006-12-28
CPC分类号： G01N1/2806
摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。
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公开(公告)号：US07504337B2
公开(公告)日：2009-03-17
申请号：US11690432
申请日：2007-03-23
IPC分类号： H01L21/461 , H01L21/302
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译： 公开了均匀地延迟IC芯片的方法。 一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。
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5.发明申请METHOD OF TEM SAMPLE PREPARATION FOR ELECTRON HOLOGRAPHY FOR SEMICONDUCTOR DEVICES 失效用于半导体器件的电子照相的TEM样品制备方法公开(公告)号：US20080156987A1
公开(公告)日：2008-07-03
申请号：US11617386
申请日：2006-12-28
IPC分类号： G01N23/04
CPC分类号： G01N1/2806
摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并且减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。
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