公开(公告)号：US07712004B1

公开(公告)日：2010-05-04

申请号：US10675002

申请日：2003-09-30

申请人： Brian K. Campbell ,  Kendell A. Chilton ,  Christopher S. MacLellan ,  Ofer Porat

发明人： Brian K. Campbell ,  Kendell A. Chilton ,  Christopher S. MacLellan ,  Ofer Porat

IPC分类号： H04L1/00

CPC分类号： H04L1/0082 ,  H04L1/0061

摘要： An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.

摘要翻译： 错误检查系统包括用于接收包括奇偶校验信息的数据元素的输入装置; 奇偶校验装置，用于检查数据元素的奇偶校验信息，以确定数据元素是否有效; 耦合到所述奇偶校验装置的CRC发生器，用于生成所述数据元素的CRC; 以及用于通过传输链路将具有奇偶校验信息和CRC的数据元素发送到下游设备的输出设备。 如果奇偶校验设备确定数据元素无效，则奇偶校验设备可操作以将错误信号输出到CRC发生器，以指示CRC发生器破坏该数据元素的CRC生成。

公开(公告)号：US07124245B1

公开(公告)日：2006-10-17

申请号：US10675039

申请日：2003-09-30

申请人： John K. Walton ,  William F. Baxter, III ,  Kendell A. Chilton ,  Daniel Castel ,  Michael Bermingham ,  James M. Guyer

发明人： John K. Walton ,  William F. Baxter, III ,  Kendell A. Chilton ,  Daniel Castel ,  Michael Bermingham ,  James M. Guyer

IPC分类号： G06F12/00

CPC分类号： G06F12/0866

摘要： A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.

公开(公告)号：US07117305B1

公开(公告)日：2006-10-03

申请号：US10180751

申请日：2002-06-26

申请人： Kendell A. Chilton

发明人： Kendell A. Chilton

IPC分类号： G06F12/00

CPC分类号： G06F12/0866

摘要： A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory.

摘要翻译： 一种系统接口，具有：适于耦合到主机/服务器的多个前端引导器; 多个后端引导器适于耦合到一组磁盘驱动器; 数据传送部分，具有高速缓冲存储器; 缓存存储器管理器; 和一个消息网络。 高速缓冲存储器耦合到多个前端和后端导向器。 消息传递网络独立于数据传送部分工作，并且耦合到多个前端和后端。 前端和后端导向器控制主计算机/服务器和磁盘驱动器组之间的数据传输，以响应通过消息传递网络在前端导向器和后端导向器之间传递的消息，以便于主机/服务器之间的数据传输 和磁盘驱动器库。 数据通过数据传输部分中的高速缓冲存储器，因为这些数据在主计算机和磁盘驱动器组之间通过。 该系统包括高速缓冲存储器管理器，其中具有用于存储维持存储在高速缓冲存储器中的数据与存储在磁盘驱动器中的数据之间的关系的映射的存储器。 高速缓冲存储器管理器在主计算机，磁盘驱动器组和高速缓冲存储器之间提供接口，用于确定导向器是否要从磁盘驱动器读取的数据或要写入磁盘驱动器的数据驻留在高速缓存中 记忆。 通过这种布置，数据传送部分中的高速缓冲存储器不承担传送导向器消息传递的任务，而是提供与数据传输部分无关的消息传递网络，从而增加了这种消息传送的工作带宽 系统界面。 此外，高速缓冲存储器不再负责评估要从盘驱动器读取的数据或要写入到磁盘驱动器的数据是否驻留在高速缓冲存储器中的任务。

公开(公告)号：US06914784B1

公开(公告)日：2005-07-05

申请号：US10180749

申请日：2002-06-26

申请人： Kendell A. Chilton ,  Natan Vishlitzky ,  Joseph Gerard Mettee, Jr. ,  Ralph L. Specht, Jr.

发明人： Kendell A. Chilton ,  Natan Vishlitzky ,  Joseph Gerard Mettee, Jr. ,  Ralph L. Specht, Jr.

IPC分类号： H05K5/00 ,  H05K7/14

CPC分类号： H05K7/1492

摘要： A cabinet having a plurality of rack mountable chassis. One portion of such chassis has directors and electrically interconnected memory and another portion of such chassis has a plurality of disk drives. The plurality of chassis are electrically interconnected to provide a data storage system interface. A first one of such chassis includes a memory and a plurality of directors. A first plurality of the directors is adapted for coupling to a host computer/server. A second one of such chassis has a plurality of disk drives. Also includes are first electrical conductors for connecting the disk drives in the second chassis to a second plurality of directors in the first one of the chassis. A third one of such chassis includes a memory and a plurality of directors. The first plurality of the directors in the third one of the chassis are adapted for coupling to the host computer/server. A fourth one of such chassis has a plurality of disk drives. Second electrical conductors are provided for connecting the disk drives in the fourth of the chassis to a second plurality of directors in the third one of the chassis. Third electrical connectors are provided for electrically the memories in the first one of the chassis and the third one of such chassis to enable the first plurality of directors and the second plurality of directors in the first and third ones of the chassis to control data transfer between a host computer/server and a bank of disk drives as such data passes through the memories the first one of the chassis and in the third one of the chassis.

摘要翻译： 具有多个机架安装底盘的机柜。 这种底盘的一部分具有引导件和电互连的存储器，并且这种底盘的另一部分具有多个盘驱动器。 多个机架电互连以提供数据存储系统接口。 这种底盘中的第一个包括存储器和多个导向器。 第一组导体适于与主计算机/服务器耦合。 这种底盘中的第二个具有多个磁盘驱动器。 还包括用于将第二机架中的盘驱动器连接到第一机架中的第二多个导向器的第一电导体。 这种底盘中的第三个包括存储器和多个导向器。 第三个机箱中的第一组导向器适于与主机/服务器耦合。 这种底盘中的第四个具有多个磁盘驱动器。 第二电导体被提供用于将第四机架中的磁盘驱动器连接到底架的第三个中的第二组导向器。 第三电连接器被提供用于电气地在底盘的第一个和这种底盘的第三个中的存储器，以使得第一和第三个引导器中的第一个多个引导器和第二个引导器能够控制 主机/服务器和作为这种数据的一组磁盘驱动器通过存储器中的第一个机箱和第三个机箱。

公开(公告)号：US07076636B1

公开(公告)日：2006-07-11

申请号：US09972284

申请日：2001-10-05

申请人： Kendell A. Chilton

发明人： Kendell A. Chilton

IPC分类号： G06F9/30 ,  G06F12/00

CPC分类号： G06F12/0871

摘要： A data storage system includes a set of storage devices, a memory circuit board that includes a cache to temporarily store copies of data elements stored in the set of storage devices, and a processor circuit board that operates as at least one of a front-end interface between an external device and the cache and a back-end interface between the cache and the set of storage devices. The memory circuit board is configured to receive, from the processor circuit board, a communication that includes a script command and a payload. The payload includes a series of individual instructions. The memory circuit board is further configured to parse the payload to identify the series of individual instructions in response to the script command, and to perform a series of operations in accordance with the identified series of individual instructions.

摘要翻译： 数据存储系统包括一组存储设备，存储器电路板，其包括用于临时存储存储在该组存储设备中的数据元素的副本的高速缓存，以及处理器电路板，其操作为前端 外部设备和高速缓存之间的接口以及缓存与存储设备组之间的后端接口。 存储器电路板被配置为从处理器电路板接收包括脚本命令和有效载荷的通信。 有效载荷包括一系列单独的指令。 存储器电路板还被配置为解析有效载荷以响应于脚本命令来识别一系列单独指令，并且根据所识别的单独指令序列执行一系列操作。

公开(公告)号：US07073024B1

公开(公告)日：2006-07-04

申请号：US10675041

申请日：2003-09-30

申请人： Kendell A. Chilton

发明人： Kendell A. Chilton

IPC分类号： G06F12/00

CPC分类号： G06F11/1076

摘要： A method for storing data on a disk drive and checking the validity of data read from such disk drive. The method includes: transmitting the data from a source thereof for storage in the disk drive through a first transmission path and transmitting a CRC together with parity associated with such data for storage in a storage medium through a second path separate from the disk drive. The data stored on the disk drive is retrieved. A CRC associated with the retrieved data is determined. The determined CRC and the CRC stored in the storage medium are compared. With such method, if data and ins associated CRC are written into the incorrect location in the disk drive, during a read an error will be detected because the CRC of the read data will not match the CRC associated with the read data stored on the storage medium.

摘要翻译： 一种用于在磁盘驱动器上存储数据并检查从这种磁盘驱动器读取的数据的有效性的方法。 该方法包括：通过第一传输路径从其源发送数据以存储在磁盘驱动器中，并且通过与该磁盘驱动器分开的第二路径，将与这些数据相关联的奇偶校验与校验相关联地发送到存储介质中。 检索存储在磁盘驱动器上的数据。 确定与检索的数据相关联的CRC。 比较存储在存储介质中的确定的CRC和CRC。 通过这种方法，如果将数据和连接关联的CRC写入磁盘驱动器中的不正确位置，则在读取期间将检测到错误，因为读取数据的CRC将不与存储在存储器上的读取数据相关联的CRC匹配 中。

公开(公告)号：US07020754B1

公开(公告)日：2006-03-28

申请号：US10022080

申请日：2001-12-13

申请人： John K. Walton ,  Kendell A. Chilton

发明人： John K. Walton ,  Kendell A. Chilton

IPC分类号： G06F12/00

CPC分类号： G06F11/2087 ,  G06F12/0866

摘要： In one embodiment, a data storage system is provided may include an input/output (I/O) controller, and first and second memory boards. The controller may receive data and a request to store the data in the system, and may include memory for initially storing the data. The first memory board may store, in response to a first memory storage request, a first copy of the data initially stored in the controller. The first memory board may provide to the controller a first status indication indicating whether the first memory board successfully stored the first copy. The second memory board may store, in response to receipt of a second memory storage request, a second copy of the data. The controller may provide a second status indication, indicating whether the request to store the data in the system was successful.

摘要翻译： 在一个实施例中，提供的数据存储系统可以包括输入/​​输出（I / O）控制器以及第一和第二存储器板。 控制器可以接收数据和将数据存储在系统中的请求，并且可以包括用于初始存储数据的存储器。 第一存储器板可以响应于第一存储器存储请求存储最初存储在控制器中的数据的第一副本。 第一存储器板可以向控制器提供指示第一存储器板是否成功存储第一副本的第一状态指示。 第二存储器板可以响应于接收到第二存储器存储请求而存储数据的第二副本。 控制器可以提供第二状态指示，指示在系统中存储数据的请求是否成功。

公开(公告)号：US06623177B1

公开(公告)日：2003-09-23

申请号：US09901534

申请日：2001-07-09

申请人： Kendell A. Chilton

发明人： Kendell A. Chilton

IPC分类号： G02B636

CPC分类号： G02B6/43 ,  G02B6/381 ,  G02B6/424 ,  G02B6/4245 ,  G02B6/4274

摘要： An electronic system having a set of circuit boards and an interconnect. Each of the set of circuit boards includes a set of fiber optic circuit board connectors. The interconnect includes (i) a first planar member, (ii) a second planar member that is substantially parallel to the first planar member, and (iii) a set of fiber optic cable assemblies. Each fiber optic cable assembly includes a fiber optic cable segment, a first fiber optic interconnect connector which fastens to one end of that fiber optic cable segment and a second fiber optic interconnect connector which fastens to another end of that fiber optic cable segment. Each fiber optic interconnect connector extends through a hole defined by one of the first and second planar members. Furthermore, each fiber optic interconnect connector is configured to engage with a fiber optic circuit board connector.

摘要翻译： 一种具有一组电路板和互连的电子系统。 该组电路板中的每一个包括一组光纤电路板连接器。 互连包括（i）第一平面构件，（ii）基本上平行于第一平面构件的第二平面构件，以及（iii）一组光纤电缆组件。 每个光纤电缆组件包括光纤电缆段，第一光纤互连连接器，其紧固到该光纤电缆段的一端，以及第二光纤互连连接器，其紧固到该光纤电缆段的另一端。 每个光纤互连连接器延伸穿过由第一和第二平面构件之一限定的孔。 此外，每个光纤互连连接器被配置为与光纤电路板连接器接合。

公开(公告)号：US07234021B1

公开(公告)日：2007-06-19

申请号：US09972314

申请日：2001-10-08

申请人： Kendell A. Chilton

发明人： Kendell A. Chilton

IPC分类号： G06F12/02

CPC分类号： G06F12/0866 ,  G06F2212/284 ,  G06F2212/303

摘要： A data storage system has disk drives, memory circuit boards to store a set of hash lists and a cache, and a front-end interface. The front-end interface is configured to receive a data element request including a disk address identifying a set of disk drive locations that stores the data element; perform a hash function on the disk address in order to generate a hash pointer; and provide a search command, the disk address and the generated hash pointer to the memory circuit boards. The memory circuit boards are configured to receive the search command, the disk address, and the hash pointer from the front-end interface; search the set of hash lists based on the hash pointer and the disk address; and provide an indication to the front-end interface indicating whether the set of hash lists includes an entry indicating that the data element resides in cache.

摘要翻译： 数据存储系统具有磁盘驱动器，用于存储一组散列表和高速缓存的存储器电路板以及前端接口。 前端接口被配置为接收包括识别存储数据元素的一组磁盘驱动器位置的磁盘地址的数据元素请求; 对磁盘地址执行散列函数，以生成散列指针; 并向存储器电路板提供搜索命令，磁盘地址和生成的散列指针。 存储器电路板被配置为从前端接口接收搜索命令，磁盘地址和散列指针; 根据哈希指针和磁盘地址搜索哈希表集合; 并向前端接口提供指示该指示是否该组散列列表包括指示数据元素驻留在高速缓存中的条目。

公开(公告)号：US07027439B1

公开(公告)日：2006-04-11

申请号：US09852580

申请日：2001-05-10

申请人： Jonathan J. Barrow ,  Kendell A. Chilton

发明人： Jonathan J. Barrow ,  Kendell A. Chilton

IPC分类号： H04L12/56

CPC分类号： H04L69/12

摘要： A data storage system has a backplane, processing circuitry and a NIC. The processing circuitry is physically connected to the backplane, and can perform block-based data access operations. The NIC has a first port that that couples to an external network, a second port that physically connects to the backplane, and control circuitry interconnected between the first port and the second port. The control circuitry can (i) receive file-based communications from the external network through the first port and provide block-based communications to the processing circuitry through the second port and the backplane in response to the file-based communications, (ii) receive block-based communications from the processing circuitry through the second port and the backplane and provide file-based communications to the external network through the first port in response to the block-based communications, and (iii) provide application server resources to operate as an application server that runs application-level programs.

摘要翻译： 数据存储系统具有背板，处理电路和NIC。 处理电路物理连接到背板，并且可以执行基于块的数据访问操作。 NIC具有耦合到外部网络的第一端口，物理地连接到背板的第二端口以及在第一端口和第二端口之间互连的控制电路。 控制电路可以（i）通过第一端口从外部网络接收基于文件的通信，并响应于基于文件的通信，通过第二端口和背板向处理电路提供基于块的通信，（ii）接收 通过第二端口和背板从处理电路的基于块的通信，并且响应于基于块的通信，通过第一端口向外部网络提供基于文件的通信，以及（iii）提供应用服务器资源以作为 运行应用程序级程序的应用程序服务器。