公开(公告)号：US07124245B1

公开(公告)日：2006-10-17

申请号：US10675039

申请日：2003-09-30

申请人： John K. Walton ,  William F. Baxter, III ,  Kendell A. Chilton ,  Daniel Castel ,  Michael Bermingham ,  James M. Guyer

发明人： John K. Walton ,  William F. Baxter, III ,  Kendell A. Chilton ,  Daniel Castel ,  Michael Bermingham ,  James M. Guyer

IPC分类号： G06F12/00

CPC分类号： G06F12/0866

摘要： A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.

公开(公告)号：US6122756A

公开(公告)日：2000-09-19

申请号：US11721

申请日：1998-02-10

申请人： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Micheal Sporer ,  Doug J. Tucker ,  Simon N. Yeung

发明人： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Micheal Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC分类号： G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F11/00

CPC分类号： G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

摘要： A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among the plurality of motherboards and a memory controller module for accessing said main memory interfacing to said motherboard communication bus. Each motherboard also includes at least one daughterboard, detachably connected to thereto. The motherboard further includes a backplane diagnostic bus interface mechanism interfacing each of the motherboards to the backplane diagnostic bus; a microcontroller for processing information and providing outputs and a test bus controller mechanism including registers therein. The system further includes a scan chain that electrically interconnects functionalities mounted on each motherboard and each of the at least one daughter board to the test bus controller; and an applications program for execution with said microcontroller. The applications program including instructions and criteria to automatically test the functionalities and electrical connections and interconnections, to automatically determine the presence of one or more faulted components and to automatically functionally remove the faulted component(s) from the computer system. Also featured is a balanced clock tree circuit that automatically and selectively supplies certain clock pulses to the logical flip/flops of an ASIC. The system further includes redundant clock generation and distribution circuitry that automatically fails to the redundant clock circuitry in the event of a failure of the normal clock source.

摘要翻译： PCT No.PCT / US96 / 13742 Sec。 371日期1998年2月10日 102（e）1998年2月10日PCT PCT 1996年8月14日PCT公布。 公开号WO97 / 07457 日期1997年2月27日一种高可用性计算机系统和方法，包括背板，具有至少一个底板通信总线和诊断总线，多个主板，每个与诊断总线接口。 每个主板还包括包括分配在多个母板中的主存储器的存储器系统和用于访问与所述主板通信总线接口的所述主存储器的存储器控​​制器模块。 每个主板还包括至少一个子板，可拆卸地连接到其上。 主板还包括背板诊断总线接口机构，将每个主板接口连接到背板诊断总线; 用于处理信息并提供输出的微控制器和包括其中的寄存器的测试总线控制器机构。 该系统还包括扫描链，其将安装在每个主板上的功能和至少一个子板中的每一个电互连到测试总线控制器; 以及用于与所述微控制器执行的应用程序。 应用程序包括自动测试功能和电气连接和互连的指令和标准，以自动确定一个或多个故障组件的存在并自动从计算机系统功能地移除故障组件。 还有一个平衡时钟树电路，可自动选择性地向ASIC的逻辑触发器提供某些时钟脉冲。 该系统还包括在正常时钟源故障的情况下自动地对冗余时钟电路故障的冗余时钟产生和分配电路。

公开(公告)号：US07454536B1

公开(公告)日：2008-11-18

申请号：US10675166

申请日：2003-09-30

申请人： John K. Walton ,  William F. Baxter, III ,  Kendell A. Chilton ,  Daniel Castel ,  Michael Bermingham ,  James M. Guyer

发明人： John K. Walton ,  William F. Baxter, III ,  Kendell A. Chilton ,  Daniel Castel ,  Michael Bermingham ,  James M. Guyer

IPC分类号： G06F3/00

CPC分类号： G06F13/387

摘要： A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

摘要翻译： 一种排队系统，其中至少一个具有出站队列的输入/输出（I / O）接口。 多个处理单元耦合到至少一个I / O接口。 每个处理单元耦合到对应的处理单元存储器。 每个处理单元存储器具有用于这种耦合处理单元的入站队列。 所述至少一个I / O接口出站队列在由一个处理单元处理之后存储返回到I / O接口的出站信息。 I / O接口创建用于存储在处理器单元存储器的入站队列中的队列索引。 I / O接口包括转换表，该表存储在多个处理单元的生产者索引的位置以及用于这些多个处理单元的消费者索引。

公开(公告)号：US4591972A

公开(公告)日：1986-05-27

申请号：US441969

申请日：1982-11-15

申请人： James M. Guyer ,  David I. Epstein ,  David L. Keating

发明人： James M. Guyer ,  David I. Epstein ,  David L. Keating

IPC分类号： G06F9/22 ,  G06F9/24 ,  G06F9/26 ,  G06F12/10 ,  G06F13/00

CPC分类号： G06F12/1027 ,  G06F9/226 ,  G06F9/24 ,  G06F9/264 ,  G06F9/268 ,  G06F2212/2515

摘要： A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

摘要翻译： 具有分离的内核，垂直和水平微代码，独立加载垂直微代码和永久驻留的内核微代码的数据处理系统以及具有双级能力的软控制台。 该系统包括具有双ALC和微码处理器的处理器以及指令处理器。 还包括具有多功能处理器存储器，多功能半字节移位器和高速前置存储器控制器的处理器。 公开了自适应微代码控制装置272，其中微指令排序是当前微指令和当前机器状态的函数273。

公开(公告)号：US4386399A

公开(公告)日：1983-05-31

申请号：US143561

申请日：1980-04-25

申请人： Edward Rasala ,  Steven Wallach ,  Carl J. Alsing ,  Kenneth D. Holberger ,  Charles J. Holland ,  Thomas West ,  James M. Guyer ,  Richard W. Coyle ,  Michael L. Ziegler ,  Michael B. Druke

发明人： Edward Rasala ,  Steven Wallach ,  Carl J. Alsing ,  Kenneth D. Holberger ,  Charles J. Holland ,  Thomas West ,  James M. Guyer ,  Richard W. Coyle ,  Michael L. Ziegler ,  Michael B. Druke

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/34 ,  G06F11/10 ,  G06F11/14 ,  G06F12/08 ,  G06F12/10 ,  G06F12/14 ,  G06F13/00 ,  G06F9/36

CPC分类号： G06F12/0857 ,  G06F11/10 ,  G06F11/14 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/14 ,  G06F9/26 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/342 ,  G06F11/106

摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

摘要翻译： 一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。 该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。 解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。 该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。 存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。

公开(公告)号：US07769928B1

公开(公告)日：2010-08-03

申请号：US11769743

申请日：2007-06-28

申请人： Nhut Tran ,  Michael Sgrosso ,  William F. Baxter, III ,  James M. Guyer

发明人： Nhut Tran ,  Michael Sgrosso ,  William F. Baxter, III ,  James M. Guyer

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/12 ,  G06F13/38

CPC分类号： G06F13/387 ,  G06F2213/0026

摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。

公开(公告)号：US5887146A

公开(公告)日：1999-03-23

申请号：US695556

申请日：1996-08-12

申请人： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

发明人： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC分类号： G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F13/00 ,  G06F1/12

CPC分类号： G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

摘要： A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

摘要翻译： 基于硬件体系结构的非常快速，高效，高度可扩展，高效率的CCNUMA处理系统，可最大限度地减少系统总线争用，通过维护强大的排序和避免重试来最大化处理进度，并实现全映射目录结构高速缓存一致性协议。 缓存相干非均匀存储器访问（CCNUMA）架构在包括由主板和两个子板组成的多个集成模块的系统中实现。 插入主板的子板每个都包含两个作业处理器（JP），高速缓存和输入/输出（I / O）功能。 直接位于主板上的是两个小型计算机系统接口（SCSI）和一个局域网（LAN）接口形式的附加集成I / O功能。 主板包括主存储器，存储器控制器（MC）和用于高速缓存一致性的目录DRAM。 主板还包括GTL背板接口逻辑，系统时钟生成和分配逻辑，以及包括用于系统初始化的微控制器的本地资源。 交叉开关将各种逻辑块连接在一起。 一个完整的主板包含2个JP子板，2个PCI扩展板和最多512 MB的主内存。 每个子板包含两个50MHz的Motorola 88110 JP复合体，具有相关联的88410缓存控制器和1MB 2级缓存。 还提供单个16 MB的第三级直写缓存，并由第三级缓存控制器控制。

公开(公告)号：US5070475A

公开(公告)日：1991-12-03

申请号：US797856

申请日：1985-11-14

申请人： Kevin B. Normoyle ,  James M. Guyer ,  Rainer Vogt ,  Anthony S. Fong

发明人： Kevin B. Normoyle ,  James M. Guyer ,  Rainer Vogt ,  Anthony S. Fong

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/38

CPC分类号： G06F9/3877 ,  G06F9/3885

摘要： A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.

摘要翻译： 一种数据处理系统，包括与中央处理单元（CPU）连接的浮点计算单元（FPU），其中CPU提供调度控制信号以通知FPU它即将执行浮点宏指令，并提供 调度地址，其在提供调度控制信号的相同操作周期期间包括其浮点微指令的起始地址。 在FPU中提供缓冲存储器以存储一个解码的宏指令的起始地址，而FPU正在执行先前解码的宏指令的微指令序列。 当缓冲区已经存在驻留在其缓冲器中的起始地址时，FPU提供控制信号，以防止CPU提供进一步的调度地址，直到缓冲区为空。 还提供了用于同步CPU和FPU操作和数据传输的其他控制信号。

公开(公告)号：US4796176A

公开(公告)日：1989-01-03

申请号：US798561

申请日：1985-11-15

申请人： Lynn W. D'Amico ,  James M. Guyer

发明人： Lynn W. D'Amico ,  James M. Guyer

IPC分类号： G06F15/16 ,  G06F13/26 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F13/26

摘要： A multiprocessor computing system is disclosed which includes a system bus, a plurality of processing units and a plurality of synchronous input/output channel controllers. A plurality of priority lines each corresponding to a processing unit are provided through each input/output channel controller in order of priority. A synchronizing signal is generated at the same time in each input/output channel controller in response to the end of an address phase on the system bus. A latch is provided in the input/output controllers which responds to the synchronizing signal by storing the condition of the priority lines and whether an interrupt is pending. In response to a broadcast interrupt origin request instruction from a processing unit, all input/output channel controllers will respond at the same time but only the one with the priority interrupt for the requesting processing unit gives a non-zero response.

摘要翻译： 公开了一种包括系统总线，多个处理单元和多个同步输入/输出通道控制器的多处理器计算系统。 通过每个输入/输出通道控制器以优先级顺序提供各自对应于处理单元的多个优先级。 响应于系统总线上的地址相位的结束，在每个输入/输出通道控制器中同时产生同步信号。 在输入/输出控制器中提供锁存器，其通过存储优先级线路的条件以及中断是否待决来响应同步信号。 响应来自处理单元的广播中断原始请求指令，所有输入/输出通道控制器将同时响应，但只有具有请求处理单元的优先级中断的那个指令给出非零响应。

公开(公告)号：US07979588B1

公开(公告)日：2011-07-12

申请号：US11769740

申请日：2007-06-28

申请人： Nhut Tran ,  Michael Sgrosso ,  James M. Guyer ,  William F. Baxter, III

发明人： Nhut Tran ,  Michael Sgrosso ,  James M. Guyer ,  William F. Baxter, III

IPC分类号： G06F15/16 ,  G06F13/42

CPC分类号： G06F13/387 ,  G06F2213/0026

摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的快速IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下通过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。